| Message ID | 1546462674-22856-1-git-send-email-skomatineni@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V3,1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config | expand |
On Wed, Jan 02, 2019 at 12:57:52PM -0800, Sowjanya Komatineni wrote: > Add pinctrl for 3V3 and 1V8 pad drive strength configuration for > Tegra210 sdmmc which has pad configuration registers in the pinmux > reigster domain. > Pad drive strengths for Tegra186 and Later are > part of SDMMC device node itself. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) Hi Rob, any chance you could take a look at this? Thanks, Thierry > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > index 32b4b4e41923..2cecdc71d94c 100644 > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > @@ -39,12 +39,16 @@ sdhci@c8000200 { > bus-width = <8>; > }; > > -Optional properties for Tegra210 and Tegra186: > +Optional properties for Tegra210, Tegra186 and Tegra194: > - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage > configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8" > for controllers supporting multiple voltage levels. The order of names > should correspond to the pin configuration states in pinctrl-0 and > pinctrl-1. > +- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for > + Tegra210 where pad config registers are in the pinmux register domain > + for pull-up-strength and pull-down-strength values configuration when > + using pads at 3V3 and 1V8 levels. > - nvidia,only-1-8-v : The presence of this property indicates that the > controller operates at a 1.8 V fixed I/O voltage. > - nvidia,pad-autocal-pull-up-offset-3v3, > -- > 2.7.4 >
On Wed, 2 Jan 2019 12:57:52 -0800, Sowjanya Komatineni wrote: > Add pinctrl for 3V3 and 1V8 pad drive strength configuration for > Tegra210 sdmmc which has pad configuration registers in the pinmux > reigster domain. > Pad drive strengths for Tegra186 and Later are > part of SDMMC device node itself. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 32b4b4e41923..2cecdc71d94c 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -39,12 +39,16 @@ sdhci@c8000200 { bus-width = <8>; }; -Optional properties for Tegra210 and Tegra186: +Optional properties for Tegra210, Tegra186 and Tegra194: - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8" for controllers supporting multiple voltage levels. The order of names should correspond to the pin configuration states in pinctrl-0 and pinctrl-1. +- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for + Tegra210 where pad config registers are in the pinmux register domain + for pull-up-strength and pull-down-strength values configuration when + using pads at 3V3 and 1V8 levels. - nvidia,only-1-8-v : The presence of this property indicates that the controller operates at a 1.8 V fixed I/O voltage. - nvidia,pad-autocal-pull-up-offset-3v3,
Add pinctrl for 3V3 and 1V8 pad drive strength configuration for Tegra210 sdmmc which has pad configuration registers in the pinmux reigster domain. Pad drive strengths for Tegra186 and Later are part of SDMMC device node itself. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)