From patchwork Tue Jan 15 19:03:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10764991 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB7FD1390 for ; Tue, 15 Jan 2019 19:03:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C7CEB2B7AE for ; Tue, 15 Jan 2019 19:03:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B55822BB3C; Tue, 15 Jan 2019 19:03:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52C132B7AE for ; Tue, 15 Jan 2019 19:03:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732232AbfAOTDz (ORCPT ); Tue, 15 Jan 2019 14:03:55 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12268 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730300AbfAOTDz (ORCPT ); Tue, 15 Jan 2019 14:03:55 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 15 Jan 2019 11:03:40 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 15 Jan 2019 11:03:54 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 15 Jan 2019 11:03:54 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 15 Jan 2019 19:03:54 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 15 Jan 2019 19:03:54 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 15 Jan 2019 19:03:54 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.52]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 15 Jan 2019 11:03:54 -0800 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , Sowjanya Komatineni Subject: [PATCH V9 1/3] dt-bindings: mmc: tegra: Add supports-cqe property Date: Tue, 15 Jan 2019 11:03:50 -0800 Message-ID: <1547579032-18314-1-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1547579020; bh=7LmrZ9OsZ3o9SobpreCnQv4ByFBfGKe0Dav4/9uMQ1U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=OyklhS21WW7hnKq/GapYowodKpduRuDAYGTNWNWyI3/2wLRAFmS9KyVI1eYFQ37M/ qwaCZ/AUqbEa3MR4fwlw2qkXWUddJbmovtuCP9pLmSg6P0Ei7L3mu8MFrSDpXXbZJ0 WAANkQo/GbR+WDzFLMXTry49rcHU8cSdno49MAOXRdrZ8VVydhQLS9p8A3+10DgnWO AORd4XkVN8k6m/8ivIcRNdUPVuNHB/7aceCs1S0f1t/Kr6U2kmzmn73/mVbkTaeRMh avvJETBj8YyZGWVUJyGlWdQhDa0RUs22znHoipzNQTHxfPf1jMggYAUnufqyCCcS/K YRZJjcHa0i8rw== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add supports-cqe optional property for Tegra SDMMC. Tegra186 and Tegra194 supports HW Command queue only on SDMMC4 controller. This property is used to identify command queue support controller in the tegra sdhci driver. Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 32b4b4e41923..fb14c2c8d7ee 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -72,6 +72,10 @@ Optional properties for Tegra210 and Tegra186: - nvidia,default-trim : Specify the default outbound clock trimmer value. - nvidia,dqs-trim : Specify DQS trim value for HS400 timing +- supports-cqe : The presence of this property indicates that the + corresponding controller supports HW command queue feature. + Tegra186 and Tegra194 has 4 SDMMC Controllers and only SDMMC4 + controller supports HW Command Queue with eMMC device. Notes on the pad calibration pull up and pulldown offset values: - The property values are drive codes which are programmed into the