@@ -284,6 +284,7 @@ static struct variant_data variant_stm32_sdmmc = {
.datactrl_blocksz = 14,
.stm32_idmabsize_mask = GENMASK(12, 5),
.init = sdmmc_variant_init,
+ .quirks = MMCI_QUIRK_STM32_DTMODE,
};
static struct variant_data variant_qcom = {
@@ -1028,6 +1029,16 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
else
datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4;
+ if (variant->quirks & MMCI_QUIRK_STM32_DTMODE) {
+ if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
+ data->blocks == 1)
+ datactrl |= MCI_DPSM_STM32_MODE_SDIO;
+ else if (data->stop && !host->mrq->sbc)
+ datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;
+ else
+ datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
+ }
+
if (data->flags & MMC_DATA_READ)
datactrl |= MCI_DPSM_DIRECTION;
@@ -131,6 +131,11 @@
/* Control register extensions in the Qualcomm versions */
#define MCI_DPSM_QCOM_DATA_PEND BIT(17)
#define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
+/* Control register extensions in STM32 versions */
+#define MCI_DPSM_STM32_MODE_BLOCK (0 << 2)
+#define MCI_DPSM_STM32_MODE_SDIO (1 << 2)
+#define MCI_DPSM_STM32_MODE_STREAM (2 << 2)
+#define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2)
#define MMCIDATACNT 0x030
#define MMCISTATUS 0x034
@@ -357,6 +362,8 @@ struct variant_data {
void (*init)(struct mmci_host *host);
};
+#define MMCI_QUIRK_STM32_DTMODE BIT(0)
+
/* mmci variant callbacks */
struct mmci_host_ops {
int (*validate_data)(struct mmci_host *host, struct mmc_data *data);