From patchwork Sat Mar 2 05:20:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836475 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5BAA817E0 for ; Sat, 2 Mar 2019 05:21:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4942C2D759 for ; Sat, 2 Mar 2019 05:21:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3CB032D789; Sat, 2 Mar 2019 05:21:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E4B352D759 for ; Sat, 2 Mar 2019 05:21:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726319AbfCBFUb (ORCPT ); Sat, 2 Mar 2019 00:20:31 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9806 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725300AbfCBFUb (ORCPT ); Sat, 2 Mar 2019 00:20:31 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:39 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 01 Mar 2019 21:20:30 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:30 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 2 Mar 2019 05:20:30 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:29 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 01/11] mmc: tegra: fix ddr signaling for non-ddr modes Date: Fri, 1 Mar 2019 21:20:15 -0800 Message-ID: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504039; bh=Qe2T48QJX1FMDt69wX/5uHHEUnqPGEOo62jpymdGE50=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=lxtcKuD+qW5/YBbhFQsOJCjhgJ5hQLM3klmDJR0v1JK69DAZQMJmJhBn0LtZ7X/3k 14wtgBydG+RPtAtxPRmdBZmW2LNEAyMjuxR7/ruiSsTvjdtKi0oTT5hGZSaoEWFo/r jMYmqj//fEEPYDELTq74RHi94V78nkG2vgypOGRprA1rNqmZ4N+Ya5Q7u4Qqi5bsag HnRsKtnJA3agieKtksQcwpJ3pm5MLab/ElebnAa+xVeIIy7H/T9TqI72cgGQmiOBkD GYiUmK+SmdnZ+cC1xfMvAknFuRqA2/oZcDpmAHma/oJVn9jb1ue6w8EruetyMVq3Io EupwgF+PDJkxQ== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ddr_signaling is set to true for DDR50 and DDR52 modes but is not set back to false for other modes. This programs incorrect host clock when mode change happens from DDR52/DDR50 to other SDR or HS modes like incase of mmc_retune where it switches from HS400 to HS DDR and then from HS DDR to HS mode and then to HS200. This patch fixes the ddr_signaling to set properly for non DDR modes. Signed-off-by: Sowjanya Komatineni Tested-by: Jon Hunter Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 32e62904c0d3..46086dd43bfb 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -779,6 +779,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, bool set_dqs_trim = false; bool do_hs400_dll_cal = false; + tegra_host->ddr_signaling = false; switch (timing) { case MMC_TIMING_UHS_SDR50: case MMC_TIMING_UHS_SDR104: