From patchwork Sat Mar 2 05:20:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 17F42922 for ; Sat, 2 Mar 2019 05:21:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 071A82D759 for ; Sat, 2 Mar 2019 05:21:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EFCE62D789; Sat, 2 Mar 2019 05:21:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B6622D759 for ; Sat, 2 Mar 2019 05:21:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728087AbfCBFUy (ORCPT ); Sat, 2 Mar 2019 00:20:54 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15121 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727985AbfCBFUx (ORCPT ); Sat, 2 Mar 2019 00:20:53 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:51 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:52 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:20:52 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:52 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:20:51 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:51 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 08/11] mmc: tegra: add Tegra186 WAR for CQE Date: Fri, 1 Mar 2019 21:20:22 -0800 Message-ID: <1551504025-3541-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504051; bh=1B+N7uE+HVqMozipQL4sMXKkt7WcnsWeT4TSmtt5PYo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=VZTRqa9sAIkv/NVS8AO5Ymz3T2BA+H6Z0Xc+Z7oQRHovXrOr3cE3LWAOvu0sckU/q Cg9CZd4K3Byo4o5OT3E2oMIYOx57fScP+sP+rqQQjgWEIQxxFbH2mTjQYVsKIHf3pP IS9VgXdNwfDBDt4SHhmOdYemgbnqxCTm5KY+Ia4YiyGB6/qogLBMkK4b+Jj8nLE34h 4vSUzMoedLOQGxlhI1GLx+OE0L15ImqV7xOUctn45GSYM0QoqJLYVmzLgwP7DKeqGR gobFcTsgi8oQxa49N9k+51gcMCqSn6X08dW959cCx/itYchCVofaCYTsp0gPoIGFd5 pfT6ltka32Wkw== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra186 design has a known bug where CQE does not generated task complete interrupt for data transfer tasks issued after DCMD task with R1b response type and results in timeout. SW WAR is to set CMD_TIMING to 1 in task descriptor for DCMDs with R1b response type. This bug and SW WAR is applicable only for Tegra186 and not for Tegra194. This patch adds this WAR to Tegra186. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2086e0eced88..2b63626dc2fa 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -116,6 +116,7 @@ struct sdhci_tegra_soc_data { u32 nvquirks; u8 min_tap_delay; u8 max_tap_delay; + u32 cqequirks; }; /* Magic pull up and pull down pad calibration offsets */ @@ -1354,6 +1355,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra186 = { NVQUIRK_ENABLE_SDR104, .min_tap_delay = 84, .max_tap_delay = 136, + .cqequirks = CQHCI_QUIRK_CMD_TIMING_R1B_DCMD, }; static const struct sdhci_tegra_soc_data soc_data_tegra194 = { @@ -1383,6 +1385,7 @@ static int sdhci_tegra_add_host(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; struct cqhci_host *cq_host; bool dma64; int ret; @@ -1407,6 +1410,7 @@ static int sdhci_tegra_add_host(struct sdhci_host *host) cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; cq_host->ops = &sdhci_tegra_cqhci_ops; + cq_host->quirks = soc_data->cqequirks; dma64 = host->flags & SDHCI_USE_64_BIT_DMA; if (dma64)