From patchwork Tue Aug 4 04:29:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11699721 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BD75A1731 for ; Tue, 4 Aug 2020 04:29:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D586522CB1 for ; Tue, 4 Aug 2020 04:29:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="r2JlNMBc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729768AbgHDE3l (ORCPT ); Tue, 4 Aug 2020 00:29:41 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:4373 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729326AbgHDE3b (ORCPT ); Tue, 4 Aug 2020 00:29:31 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 03 Aug 2020 21:28:42 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 03 Aug 2020 21:29:31 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 03 Aug 2020 21:29:31 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 4 Aug 2020 04:29:27 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 4 Aug 2020 04:29:27 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.221]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 03 Aug 2020 21:29:27 -0700 From: Sowjanya Komatineni To: , , , , CC: , , , , Subject: [PATCH v2 1/6] sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra210 Date: Mon, 3 Aug 2020 21:29:18 -0700 Message-ID: <1596515363-27235-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596515363-27235-1-git-send-email-skomatineni@nvidia.com> References: <1596515363-27235-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596515322; bh=GRxAVl1MNmeG00GyZSeX3lvvDJtcrM+1khuxn73XwQg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=r2JlNMBcla7AEgGlcKJGKoAaosyEeJK/cQ7Opd4ibfgwzHz1pefLY7clMKcEJmtQJ RVpkjYOR1fbpob1mMuGxK8xrJezOVoIe3XtplMV1a3iM8gu4jA/EiXhv1ZeFlj/LNE fRQF2IwmbU0R1Y4AJcsnY0/ciMgqc5vcChnkEtOwrDB8g8jgR0K7QiI4BscyQrTo5Z cov/r/Zfz1oKNupKOmkglgUORz4O+ojsDvqVTjPt505e0irXWngPlx/VJTaZtPUONs urLPokdg62+ZwjVz16Zr0U53rCbpDbN4d2+v9oGGpq1uiGF2kJY01NZ/AK4rFeaK71 8LsYvpkM1kVNg== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support") SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set for Tegra210 from the beginning of Tegra210 support in the driver. Tegra210 SDMMC hardware by default uses timeout clock (TMCLK) instead of SDCLK and this quirk should not be set. So, this patch remove this quirk for Tegra210. Signed-off-by: Sowjanya Komatineni Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 0a3f9d0..2be3511 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1418,7 +1418,6 @@ static const struct sdhci_ops tegra210_sdhci_ops = { static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | - SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |