| Message ID | 1a7f7f0941314da66acda3c60f44b3d2417133e6.1585827904.git.mirq-linux@rere.qmqm.pl (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | SDHCI clock handling fixes and cleanups | expand |
Hi "Michał,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on next-20200403]
[cannot apply to xlnx/master v5.6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Micha-Miros-aw/SDHCI-clock-handling-fixes-and-cleanups/20200403-132632
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git bef7b2a7be28638770972ab2709adf11d601c11a
config: x86_64-randconfig-s2-20200403 (attached as .config)
compiler: gcc-5 (Ubuntu 5.5.0-12ubuntu1) 5.5.0 20171010
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/mmc/host/sdhci.o: warning: objtool: sdhci_calc_clk() falls through to next function sdhci_set_clock()
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On Fri, Apr 03, 2020 at 09:02:35PM +0800, kbuild test robot wrote: [...] > Reported-by: kbuild test robot <lkp@intel.com> > > All warnings (new ones prefixed by >>): > > >> drivers/mmc/host/sdhci.o: warning: objtool: sdhci_calc_clk() falls through to next function sdhci_set_clock() This looks like false positive, as there is 'return clk;' at the function's end untouched by the patches. Best Regards, Michał Mirosław
On 2/04/20 2:54 pm, Michał Mirosław wrote: > Make clock frequency calculations simpler by replacing loops > with divide-and-clamp. I am sorry, but I am not really sure the simplification is worth the code churn, risk of introducing new bugs, or validation effort. IMO, the loops, while perhaps inefficient, are not hard to understand. > > Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> > --- > drivers/mmc/host/sdhci.c | 56 +++++++++++++++++++--------------------- > drivers/mmc/host/sdhci.h | 4 +-- > 2 files changed, 29 insertions(+), 31 deletions(-) > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > index ed88ac4e4cf3..d750c0997c3f 100644 > --- a/drivers/mmc/host/sdhci.c > +++ b/drivers/mmc/host/sdhci.c > @@ -1756,10 +1756,13 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host) > u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, > unsigned int *actual_clock) > { > - int div = 0; /* Initialized for compiler warning */ > + unsigned int div = 0; /* Initialized for compiler warning */ > int real_div = div, clk_mul = 1; > u16 clk = 0; > - bool switch_base_clk = false; > + bool use_base_clk; > + > + if (clock == 0) > + unreachable(); > > if (host->version >= SDHCI_SPEC_300) { > if (host->preset_enabled) { > @@ -1781,13 +1784,12 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, > * Check if the Host Controller supports Programmable Clock > * Mode. > */ > - if (host->clk_mul) { > - for (div = 1; div <= 1024; div++) { > - if ((host->max_clk * host->clk_mul / div) > - <= clock) > - break; > - } > - if ((host->max_clk * host->clk_mul / div) <= clock) { > + use_base_clk = !host->clk_mul; > + > + if (!use_base_clk) { > + div = DIV_ROUND_UP(host->max_clk * host->clk_mul, clock); > + > + if (div <= SDHCI_MAX_DIV_SPEC_300 / 2 + 1) { > /* > * Set Programmable Clock Mode in the Clock > * Control register. > @@ -1798,35 +1800,31 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, > div--; > } else { > /* > - * Divisor can be too small to reach clock > - * speed requirement. Then use the base clock. > + * Divisor is too big for requested clock rate. > + * Use the base clock, then. > */ > - switch_base_clk = true; > + use_base_clk = true; > } > } > > - if (!host->clk_mul || switch_base_clk) { > - /* Version 3.00 divisors must be a multiple of 2. */ > - if (host->max_clk <= clock) { > - div = 1; > - if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) > - div = 2; > - } else { > - for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; > - div += 2) { > - if ((host->max_clk / div) <= clock) > - break; > - } > + if (use_base_clk) { > + /* Version 3.00 divisors must be 1 or a multiple of 2. */ > + div = DIV_ROUND_UP(host->max_clk, clock); > + if (div > 1) { > + div = min(div, SDHCI_MAX_DIV_SPEC_300); > + div = round_up(div, 2); > } > - real_div = div; > div >>= 1; > + if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) > + div += !div; > + > + real_div = div * 2 + !div; > } > } else { > /* Version 2.00 divisors must be a power of 2. */ > - for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { > - if ((host->max_clk / div) <= clock) > - break; > - } > + div = DIV_ROUND_UP(host->max_clk, clock); > + div = min(div, SDHCI_MAX_DIV_SPEC_200); > + div = roundup_pow_of_two(div); > real_div = div; > div >>= 1; > } > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h > index 79dffbb731d3..ea8aabb3bf16 100644 > --- a/drivers/mmc/host/sdhci.h > +++ b/drivers/mmc/host/sdhci.h > @@ -290,8 +290,8 @@ > * End of controller registers. > */ > > -#define SDHCI_MAX_DIV_SPEC_200 256 > -#define SDHCI_MAX_DIV_SPEC_300 2046 > +#define SDHCI_MAX_DIV_SPEC_200 256u > +#define SDHCI_MAX_DIV_SPEC_300 2046u > > /* > * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. >
On Wed, Apr 15, 2020 at 04:54:33PM +0300, Adrian Hunter wrote: > On 2/04/20 2:54 pm, Michał Mirosław wrote: > > Make clock frequency calculations simpler by replacing loops > > with divide-and-clamp. > > I am sorry, but I am not really sure the simplification is worth the code > churn, risk of introducing new bugs, or validation effort. > > IMO, the loops, while perhaps inefficient, are not hard to understand. I guess this is a kind of religious subject. ;-) I tend to prefer shorter and less-branchy code. Best Regards, Michał Mirosław
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ed88ac4e4cf3..d750c0997c3f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1756,10 +1756,13 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host) u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock) { - int div = 0; /* Initialized for compiler warning */ + unsigned int div = 0; /* Initialized for compiler warning */ int real_div = div, clk_mul = 1; u16 clk = 0; - bool switch_base_clk = false; + bool use_base_clk; + + if (clock == 0) + unreachable(); if (host->version >= SDHCI_SPEC_300) { if (host->preset_enabled) { @@ -1781,13 +1784,12 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, * Check if the Host Controller supports Programmable Clock * Mode. */ - if (host->clk_mul) { - for (div = 1; div <= 1024; div++) { - if ((host->max_clk * host->clk_mul / div) - <= clock) - break; - } - if ((host->max_clk * host->clk_mul / div) <= clock) { + use_base_clk = !host->clk_mul; + + if (!use_base_clk) { + div = DIV_ROUND_UP(host->max_clk * host->clk_mul, clock); + + if (div <= SDHCI_MAX_DIV_SPEC_300 / 2 + 1) { /* * Set Programmable Clock Mode in the Clock * Control register. @@ -1798,35 +1800,31 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, div--; } else { /* - * Divisor can be too small to reach clock - * speed requirement. Then use the base clock. + * Divisor is too big for requested clock rate. + * Use the base clock, then. */ - switch_base_clk = true; + use_base_clk = true; } } - if (!host->clk_mul || switch_base_clk) { - /* Version 3.00 divisors must be a multiple of 2. */ - if (host->max_clk <= clock) { - div = 1; - if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) - div = 2; - } else { - for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; - div += 2) { - if ((host->max_clk / div) <= clock) - break; - } + if (use_base_clk) { + /* Version 3.00 divisors must be 1 or a multiple of 2. */ + div = DIV_ROUND_UP(host->max_clk, clock); + if (div > 1) { + div = min(div, SDHCI_MAX_DIV_SPEC_300); + div = round_up(div, 2); } - real_div = div; div >>= 1; + if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) + div += !div; + + real_div = div * 2 + !div; } } else { /* Version 2.00 divisors must be a power of 2. */ - for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { - if ((host->max_clk / div) <= clock) - break; - } + div = DIV_ROUND_UP(host->max_clk, clock); + div = min(div, SDHCI_MAX_DIV_SPEC_200); + div = roundup_pow_of_two(div); real_div = div; div >>= 1; } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 79dffbb731d3..ea8aabb3bf16 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -290,8 +290,8 @@ * End of controller registers. */ -#define SDHCI_MAX_DIV_SPEC_200 256 -#define SDHCI_MAX_DIV_SPEC_300 2046 +#define SDHCI_MAX_DIV_SPEC_200 256u +#define SDHCI_MAX_DIV_SPEC_300 2046u /* * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
Make clock frequency calculations simpler by replacing loops with divide-and-clamp. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> --- drivers/mmc/host/sdhci.c | 56 +++++++++++++++++++--------------------- drivers/mmc/host/sdhci.h | 4 +-- 2 files changed, 29 insertions(+), 31 deletions(-)