From patchwork Wed Aug 31 16:23:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 9307519 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6E2D260487 for ; Wed, 31 Aug 2016 16:26:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5F6D428EAF for ; Wed, 31 Aug 2016 16:26:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 53F5D28FAF; Wed, 31 Aug 2016 16:26:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6E14E28FB0 for ; Wed, 31 Aug 2016 16:26:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935544AbcHaQYV (ORCPT ); Wed, 31 Aug 2016 12:24:21 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:36470 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030333AbcHaQX2 (ORCPT ); Wed, 31 Aug 2016 12:23:28 -0400 Received: by mail-wm0-f68.google.com with SMTP id i138so8314601wmf.3; Wed, 31 Aug 2016 09:23:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=k2vrJyfhw1Z/qeBOKf8fNPzogu1S6fWCMpTbx8S7Xug=; b=x2mxxIjP1VCdiA9NH38vIXZpEVqP8Y3MVVHZu3UWBweRr5wU8oELy1Bn4DYIcxGAlG KZBMYAVwBRDnTXJpmxrTObKvOA4VkdWui+4Jpfz0+4NxO0oKxOc+8OmB8wjrdTTP4cVT qLh1jz/UqTdPspa7qLjdwIOF17lGiAV/TWjCMyu3TQhLdO8T9zTrj5GQTO+73NQ4Dz7q lbCXgGuFBVBlTHZH4lv7I/5dmpZn5z6HyD50/DXzbU9dIDHh3ZKnr5DgiYLaqTEIw5+/ yd+Ysc2Yu/6qS+o/3kMQELxzsht//ek/iC3cBJ1fq59PmSaoBVIA+YvLWNHLTNIma4zq CSsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=k2vrJyfhw1Z/qeBOKf8fNPzogu1S6fWCMpTbx8S7Xug=; b=M8zl6ph//R0WPus1fXUciG9TVYtXyyHu1B+NMyovepUJfkznu/FIseZc5ttXu9ACSC Vk7GmaNDzJqfA4H5+9a1jWcfIsjd3kI1P7vT5CUv+KDU8yJa0Zh+K0CfGxaQTK5nDYXX gJwggCDXMg2VDeQ+nrpocR4XoQF0U4rLKxc1mrJa4qOdo2G9I29aipC5TCpwLXCbQbMM 5KeekLLjERi9bfhmYA5MivZDXWE9auYeM8HYD9YZi1i/AK3KTonpLw1fHzhW4moy3uUy 2cFyXtMhUDoNtT4lU8GRfqOUHqKv57neeAmeC3lTLbIn5CL9ariqgpmFCszofH19dI5G IFdg== X-Gm-Message-State: AE9vXwPGcWHj6su4fPZgFQ0fnjdNBs4y7OJSkrAjqeifmk0Jpgrfmq9+b+55Y534Y2xoTg== X-Received: by 10.194.56.193 with SMTP id c1mr6472145wjq.167.1472660606350; Wed, 31 Aug 2016 09:23:26 -0700 (PDT) Received: from localhost (port-10228.pppoe.wtnet.de. [84.46.40.28]) by smtp.gmail.com with ESMTPSA id g1sm638789wjy.5.2016.08.31.09.23.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Aug 2016 09:23:25 -0700 (PDT) From: Thierry Reding To: Adrian Hunter , Ulf Hansson Cc: Paul Kocialkowski , linux-mmc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH] mmc: tegra: Mark 64-bit DMA broken on Tegra124 Date: Wed, 31 Aug 2016 18:23:24 +0200 Message-Id: <20160831162324.15480-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.9.3 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding According to the TRM, the SD/MMC controller on Tegra124 supports 34-bit addressing, but testing shows that this doesn't work. On a device which has more than 2 GiB of RAM and LPAE enabled, buffer allocations can use addresses above the 32-bit boundary. One way to work around this would be to enable IOMMU physical to virtual address translations for the SD/MMC controllers, but that's not easy to implement without breaking existing use-cases. It's also not obvious why 34-bit addressing doesn't work as advertised. In order to fix this for existing users, add the SDHCI_QUIRK2_BROKEN_64_BIT_DMA quirk for now. Reported-by: Paul Kocialkowski Signed-off-by: Thierry Reding Acked-by: Stephen Warren Acked-by: Arnd Bergmann Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index d89200ee017e..a3d045630d0c 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -394,6 +394,22 @@ static const struct sdhci_tegra_soc_data soc_data_tegra114 = { .pdata = &sdhci_tegra114_pdata, }; +static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { + .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | + SDHCI_QUIRK_SINGLE_POWER_WRITE | + SDHCI_QUIRK_NO_HISPD_BIT | + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_BROKEN_64_BIT_DMA, + .ops = &tegra114_sdhci_ops, +}; + +static const struct sdhci_tegra_soc_data soc_data_tegra124 = { + .pdata = &sdhci_tegra124_pdata, +}; + static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | @@ -427,7 +443,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra186 = { static const struct of_device_id sdhci_tegra_dt_match[] = { { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, - { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, + { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },