From patchwork Mon Feb 5 12:50:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 10200221 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B1F5160247 for ; Mon, 5 Feb 2018 12:51:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2685286BE for ; Mon, 5 Feb 2018 12:51:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9694A2871B; Mon, 5 Feb 2018 12:51:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF471286BE for ; Mon, 5 Feb 2018 12:51:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752844AbeBEMvZ (ORCPT ); Mon, 5 Feb 2018 07:51:25 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:29225 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752710AbeBEMvX (ORCPT ); Mon, 5 Feb 2018 07:51:23 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w15CopWq010644; Mon, 5 Feb 2018 06:50:51 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517835051; bh=rhq1UgDeYXGmwkXgj61euVRB2BeHSvMpe/lz1CD6Si8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ohzvNRZen3fKaDCzQHKBpZOh8lFjwhOmYVxH9t/WUtqHsWQsgsfWx9zQ3tz3bwQCO NvJxYHDlSr7VdOXN/m/nkxyZzGIo6o6kc+ycKLscE/O1QfmA4GGajqgu33+PBVrEmd cNVFrldyzGP4aXRCYxJ2UhdID9GDfYQZ6ogm0go8= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CopTd019716; Mon, 5 Feb 2018 06:50:51 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 5 Feb 2018 06:50:51 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 5 Feb 2018 06:50:51 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CoaGY023963; Mon, 5 Feb 2018 06:50:48 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Adrian Hunter CC: Rob Herring , Mark Rutland , Russell King , Kishon Vijay Abraham I , , , , , Subject: [PATCH v2 03/16] mmc: sdhci-omap: Add custom set_uhs_signaling sdhci_host ops Date: Mon, 5 Feb 2018 18:20:16 +0530 Message-ID: <20180205125029.21570-4-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205125029.21570-1-kishon@ti.com> References: <20180205125029.21570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP UHS-1 DDR50 and MMC DDR52 mode require DDR bit to be set in the configuration register (MMCHS_CON). Add sdhci-omap specific set_uhs_signaling ops to set this bit. Also while setting the UHSMS bit, clock should be disabled. Signed-off-by: Kishon Vijay Abraham I Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-omap.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index df927f3faaf6..86b6cc0a5380 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -31,6 +31,7 @@ #define SDHCI_OMAP_CON 0x12c #define CON_DW8 BIT(5) #define CON_DMA_MASTER BIT(20) +#define CON_DDR BIT(19) #define CON_CLKEXTFREE BIT(16) #define CON_PADEN BIT(15) #define CON_INIT BIT(1) @@ -461,6 +462,26 @@ static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode) enable_irq(host->irq); } +static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u32 reg; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + + sdhci_omap_stop_clock(omap_host); + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) + reg |= CON_DDR; + else + reg &= ~CON_DDR; + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); + + sdhci_set_uhs_signaling(host, timing); + sdhci_omap_start_clock(omap_host); +} + static struct sdhci_ops sdhci_omap_ops = { .set_clock = sdhci_omap_set_clock, .set_power = sdhci_omap_set_power, @@ -470,7 +491,7 @@ static struct sdhci_ops sdhci_omap_ops = { .set_bus_width = sdhci_omap_set_bus_width, .platform_send_init_74_clocks = sdhci_omap_init_74_clocks, .reset = sdhci_reset, - .set_uhs_signaling = sdhci_set_uhs_signaling, + .set_uhs_signaling = sdhci_omap_set_uhs_signaling, }; static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)