diff mbox series

mmc: tmio: more concise clk calculation

Message ID 20180830121438.12588-1-wsa+renesas@sang-engineering.com (mailing list archive)
State New, archived
Headers show
Series mmc: tmio: more concise clk calculation | expand

Commit Message

Wolfram Sang Aug. 30, 2018, 12:14 p.m. UTC
Concise, but still readable.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/mmc/host/tmio_mmc.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

Comments

Ulf Hansson Aug. 30, 2018, 12:30 p.m. UTC | #1
On 30 August 2018 at 14:14, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Concise, but still readable.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Applied for next, thanks!

Kind regards
Uffe

> ---
>  drivers/mmc/host/tmio_mmc.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
> index 0ae9ba1ee01b..0ae100e62b57 100644
> --- a/drivers/mmc/host/tmio_mmc.c
> +++ b/drivers/mmc/host/tmio_mmc.c
> @@ -56,14 +56,9 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
>
>         divisor = host->pdata->hclk / new_clock;
>
> -       if (divisor <= 1) {
> -               clk_sel = 1;
> -               clk = 0;
> -       } else {
> -               clk_sel = 0;
> -               /* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */
> -               clk = roundup_pow_of_two(divisor) >> 2;
> -       }
> +       /* bit7 set: 1/512, ... bit0 set: 1/4, all bits clear: 1/2 */
> +       clk_sel = (divisor <= 1);
> +       clk = clk_sel ? 0 : (roundup_pow_of_two(divisor) >> 2);
>
>         host->pdata->set_clk_div(host->pdev, clk_sel);
>
> --
> 2.11.0
>
diff mbox series

Patch

diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index 0ae9ba1ee01b..0ae100e62b57 100644
--- a/drivers/mmc/host/tmio_mmc.c
+++ b/drivers/mmc/host/tmio_mmc.c
@@ -56,14 +56,9 @@  static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
 
 	divisor = host->pdata->hclk / new_clock;
 
-	if (divisor <= 1) {
-		clk_sel = 1;
-		clk = 0;
-	} else {
-		clk_sel = 0;
-		/* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */
-		clk = roundup_pow_of_two(divisor) >> 2;
-	}
+	/* bit7 set: 1/512, ... bit0 set: 1/4, all bits clear: 1/2 */
+	clk_sel = (divisor <= 1);
+	clk = clk_sel ? 0 : (roundup_pow_of_two(divisor) >> 2);
 
 	host->pdata->set_clk_div(host->pdev, clk_sel);