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Fri, 28 Dec 2018 03:26:10 +0000 Received: from VI1PR04MB5040.eurprd04.prod.outlook.com ([fe80::cd3d:ce97:132b:7148]) by VI1PR04MB5040.eurprd04.prod.outlook.com ([fe80::cd3d:ce97:132b:7148%3]) with mapi id 15.20.1471.019; Fri, 28 Dec 2018 03:26:10 +0000 From: BOUGH CHEN To: "ulf.hansson@linaro.org" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "adrian.hunter@intel.com" , "rmk+kernel@armlinux.org.uk" CC: Fabio Estevam , dl-linux-imx , "linux-mmc@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH v2 2/3] mmc: sdhci-esdhc-imx: add SD clock limitation for imx6ull Thread-Topic: [PATCH v2 2/3] mmc: sdhci-esdhc-imx: add SD clock limitation for imx6ull Thread-Index: AQHUnl0Tx2I9di4OK0SPJzvWAKhVnA== Date: Fri, 28 Dec 2018 03:26:10 +0000 Message-ID: <20181228033323.32308-2-haibo.chen@nxp.com> References: <20181228033323.32308-1-haibo.chen@nxp.com> In-Reply-To: <20181228033323.32308-1-haibo.chen@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.17.1 x-clientproxiedby: HK2PR02CA0141.apcprd02.prod.outlook.com (2603:1096:202:16::25) To VI1PR04MB5040.eurprd04.prod.outlook.com (2603:10a6:803:59::33) authentication-results: spf=none (sender IP is ) smtp.mailfrom=haibo.chen@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: k2FRwqp1Mo7rF/xzxjpS24Q3x0DJIbjpWquUcx+3ovZT4aWkjj8Teyf57Jdt9+ZQ2Oa12zgyH3an+RamJZSUwDMo0N4Dhki20txHf6GcHcH8kLOJrm07lFtJOHhV4bQ5m8rEzWnmtZlhq2pfTsceyVErRL7lqr2/ujy6wOq7ECr8wnESsgBDGqFKtCttlh2KP5nmyE+nsn3SP7qQl6RziYLVdjPXlibBUnJ4/Qkvsa7nwYPTxFMkzzpqAV5nGc3h1iqf8ut8AW44xpraWZh++quV88ifdwoC1K5JPSP7gFwFArhXZRWm6eg3UWixF40x spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ad826683-c679-4060-7e8d-08d66c743631 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Dec 2018 03:26:10.3925 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6047 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP i.MX6ULL has errata ERR010450, point out that due to SOC I/O timing limitation, for eMMC HS200 and SD/SDIO 3.0 SDR104, the clock rate can't exceed 150MHz. And for eMMC DDR52 and SD/SDIO DDR50 mode, the clock rate can't exceed 45MHz. This patch add this limit for imx6ull. Signed-off-by: Haibo Chen Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-esdhc-imx.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 7cfcc8618e45..e1d9b2985979 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -138,7 +138,11 @@ #define ESDHC_FLAG_HS200 BIT(8) /* The IP supports HS400 mode */ #define ESDHC_FLAG_HS400 BIT(9) - +/* The IP has errata ERR010450 + * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't + * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. + */ +#define ESDHC_FLAG_ERR010450 BIT(10) /* A clock frequency higher than this rate requires strobe dll control */ #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 @@ -177,6 +181,12 @@ static struct esdhc_soc_data usdhc_imx6sx_data = { | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, }; +static struct esdhc_soc_data usdhc_imx6ull_data = { + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 + | ESDHC_FLAG_ERR010450, +}; + static struct esdhc_soc_data usdhc_imx7d_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 @@ -227,6 +237,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = { { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, + { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, { /* sentinel */ } }; @@ -733,6 +744,14 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, | ESDHC_CLOCK_MASK); sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); + if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { + unsigned int max_clock; + + max_clock = imx_data->is_ddr ? 45000000 : 150000000; + + clock = min(clock, max_clock); + } + while (host_clock / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) pre_div *= 2;