| Message ID | 20190610185354.35310-2-rrangel@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning | expand |
On 10/06/19 9:53 PM, Raul E Rangel wrote: > The O2 controller supports 8-bit EMMC access. mmc_select_bus_width() > will be used to determine if the MMC supports 8-bit or 4-bit access. The problem is that the bit indicates a host controller capability, not how many data lines there actually are on the board. Will this break something that does not have 8 lines? > > Signed-off-by: Raul E Rangel <rrangel@chromium.org> > --- > I tested this on an AMD chromebook. > > $ cat /sys/kernel/debug/mmc1/ios > clock: 200000000 Hz > actual clock: 200000000 Hz > vdd: 21 (3.3 ~ 3.4 V) > bus mode: 2 (push-pull) > chip select: 0 (don't care) > power mode: 2 (on) > bus width: 3 (8 bits) > timing spec: 9 (mmc HS200) > signal voltage: 1 (1.80 V) > driver type: 0 (driver type B) > > Before this patch only 4 bit was negotiated. > > drivers/mmc/host/sdhci-pci-o2micro.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c > index dd21315922c87..07bb91cbdf1f8 100644 > --- a/drivers/mmc/host/sdhci-pci-o2micro.c > +++ b/drivers/mmc/host/sdhci-pci-o2micro.c > @@ -395,11 +395,16 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) > { > struct sdhci_pci_chip *chip; > struct sdhci_host *host; > - u32 reg; > + u32 reg, caps; > int ret; > > chip = slot->chip; > host = slot->host; > + > + caps = sdhci_readl(host, SDHCI_CAPABILITIES); > + if (caps & SDHCI_CAN_DO_8BIT) > + host->mmc->caps |= MMC_CAP_8_BIT_DATA; > + > switch (chip->pdev->device) { > case PCI_DEVICE_ID_O2_SDS0: > case PCI_DEVICE_ID_O2_SEABIRD0: >
On Wed, Jun 12, 2019 at 04:09:47PM +0300, Adrian Hunter wrote: > On 10/06/19 9:53 PM, Raul E Rangel wrote: > > The O2 controller supports 8-bit EMMC access. mmc_select_bus_width() > > will be used to determine if the MMC supports 8-bit or 4-bit access. > > The problem is that the bit indicates a host controller capability, not how > many data lines there actually are on the board. Will this break something > that does not have 8 lines? So I asked the controller vendor about that: > The capability shows the host controller can support 1,4,and 8 bit bus > data transfer but it also depends on if HW can support it. Driver or FW > should implement the bus testing procedure that is defined in A.6.3.a > in JESD84-B51 spec to decide the real bus width that is supported in HW. This seems to be what `mmc_select_bus_width()` is doing. I don't actually have any 4-bit hardware to test with though. Thanks for the review!
On 12/06/19 6:08 PM, Raul Rangel wrote: > On Wed, Jun 12, 2019 at 04:09:47PM +0300, Adrian Hunter wrote: >> On 10/06/19 9:53 PM, Raul E Rangel wrote: >>> The O2 controller supports 8-bit EMMC access. mmc_select_bus_width() >>> will be used to determine if the MMC supports 8-bit or 4-bit access. >> >> The problem is that the bit indicates a host controller capability, not how >> many data lines there actually are on the board. Will this break something >> that does not have 8 lines? > > So I asked the controller vendor about that: >> The capability shows the host controller can support 1,4,and 8 bit bus >> data transfer but it also depends on if HW can support it. Driver or FW >> should implement the bus testing procedure that is defined in A.6.3.a >> in JESD84-B51 spec to decide the real bus width that is supported in HW. > > This seems to be what `mmc_select_bus_width()` is doing. Good point. Can you add this information to the commit message and add a comment in the code. > > I don't actually have any 4-bit hardware to test with though. > > Thanks for the review! >
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c index dd21315922c87..07bb91cbdf1f8 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -395,11 +395,16 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) { struct sdhci_pci_chip *chip; struct sdhci_host *host; - u32 reg; + u32 reg, caps; int ret; chip = slot->chip; host = slot->host; + + caps = sdhci_readl(host, SDHCI_CAPABILITIES); + if (caps & SDHCI_CAN_DO_8BIT) + host->mmc->caps |= MMC_CAP_8_BIT_DATA; + switch (chip->pdev->device) { case PCI_DEVICE_ID_O2_SDS0: case PCI_DEVICE_ID_O2_SEABIRD0:
The O2 controller supports 8-bit EMMC access. mmc_select_bus_width() will be used to determine if the MMC supports 8-bit or 4-bit access. Signed-off-by: Raul E Rangel <rrangel@chromium.org> --- I tested this on an AMD chromebook. $ cat /sys/kernel/debug/mmc1/ios clock: 200000000 Hz actual clock: 200000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 9 (mmc HS200) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) Before this patch only 4 bit was negotiated. drivers/mmc/host/sdhci-pci-o2micro.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)