From patchwork Fri Jul 26 02:07:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael K. Johnson" X-Patchwork-Id: 11060119 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DCA8B912 for ; Fri, 26 Jul 2019 02:07:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CBAA328A33 for ; Fri, 26 Jul 2019 02:07:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BF61028A6B; Fri, 26 Jul 2019 02:07:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E810328A33 for ; Fri, 26 Jul 2019 02:07:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726099AbfGZCHt (ORCPT ); Thu, 25 Jul 2019 22:07:49 -0400 Received: from esa01.kjsl.com ([198.137.202.87]:3095 "EHLO esa01.kjsl.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725838AbfGZCHs (ORCPT ); Thu, 25 Jul 2019 22:07:48 -0400 Received: from unknown (HELO people.danlj.org) ([IPv6:2607:7c80:54:5:7609:68e3:940d:b47c]) by esa01.kjsl.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jul 2019 02:07:47 +0000 Received: from people.danlj.org (localhost [127.0.0.1]) by people.danlj.org (8.14.7/8.14.7) with ESMTP id x6Q27lOp012093 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 25 Jul 2019 22:07:47 -0400 Received: (from johnsonm@localhost) by people.danlj.org (8.14.7/8.15.2/Submit) id x6Q27k8j012092; Thu, 25 Jul 2019 22:07:46 -0400 Date: Thu, 25 Jul 2019 22:07:46 -0400 From: "Michael K. Johnson" To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Ben Chuang Subject: [PATCH v2 1/2] mmc: sdhci: Add PLL Enable support to internal clock setup Message-ID: <20190726020746.GB12042@people.danlj.org> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. This changes the timeouts to the new specification of 150ms for each step and is documented as safe for "prior versions which do not support PLL Enable." Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 59acf8e3331e..14957578bf2e 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1636,8 +1636,8 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - /* Wait max 20 ms */ - timeout = ktime_add_ms(ktime_get(), 20); + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); while (1) { bool timedout = ktime_after(ktime_get(), timeout); @@ -1650,7 +1650,28 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) sdhci_dumpregs(host); return; } - udelay(10); + usleep_range(10,15); + } + + clk |= SDHCI_CLOCK_PLL_EN; + clk &= ~SDHCI_CLOCK_INT_STABLE; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { + pr_err("%s: PLL clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + usleep_range(10,15); } clk |= SDHCI_CLOCK_CARD_EN; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 199712e7adbb..72601a4d2e95 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -114,6 +114,7 @@ #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 #define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_PLL_EN 0x0008 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001