From patchwork Tue Dec 3 20:33:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 11271895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8CADD13A4 for ; Tue, 3 Dec 2019 20:33:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6908020848 for ; Tue, 3 Dec 2019 20:33:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727118AbfLCUdI (ORCPT ); Tue, 3 Dec 2019 15:33:08 -0500 Received: from sauhun.de ([88.99.104.3]:34616 "EHLO pokefinder.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726567AbfLCUdI (ORCPT ); Tue, 3 Dec 2019 15:33:08 -0500 Received: from localhost (p54B33759.dip0.t-ipconnect.de [84.179.55.89]) by pokefinder.org (Postfix) with ESMTPSA id A31C62C0667; Tue, 3 Dec 2019 21:33:06 +0100 (CET) From: Wolfram Sang To: linux-mmc@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda , Wolfram Sang Subject: [RFC PATCH 2/2] mmc: renesas_sdhi: enfore manual correction for Gen3 Date: Tue, 3 Dec 2019 21:33:00 +0100 Message-Id: <20191203203301.2202-3-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191203203301.2202-1-wsa+renesas@sang-engineering.com> References: <20191203203301.2202-1-wsa+renesas@sang-engineering.com> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org HW engineers say that automatic tap correction cannot be used for HS400 in all R-Car Gen3 SoCs. So, check for that SDHI variant and disable it when HS400 is about to be enabled. Signed-off-by: Wolfram Sang Reviewed-by: Yoshihiro Shimoda --- The BSP handles this differently and adds a quirk entry to every soc_device_match and checks the quirk entry. I chose this less intrusive method because all Gen3 SoCs are affected. But not all SDHI instances, only those which can access eMMC, of course. So, I likes this approach a tad better. If you think all quirks should be centralized in the quirks structure, I am open for discussion. drivers/mmc/host/renesas_sdhi_core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 903da3ba399b..a29290ee2051 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -343,6 +343,12 @@ static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host) sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos_hs400); + /* Gen3 can't do automatic tap correction with HS400, so disable it */ + if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, + ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |