From patchwork Wed Aug 12 13:01:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 11710781 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DBDAD13B6 for ; Wed, 12 Aug 2020 13:03:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF39E20885 for ; Wed, 12 Aug 2020 13:03:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="YgD/uDEt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727981AbgHLNCj (ORCPT ); Wed, 12 Aug 2020 09:02:39 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:27081 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727943AbgHLNCj (ORCPT ); Wed, 12 Aug 2020 09:02:39 -0400 X-UUID: 3bf25b47e65d41b185baced8352ecaf0-20200812 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=J+qTrluFnbm8L24nMFqbLJeAwO3aSNUSuAOeF4ndDNg=; b=YgD/uDEtaEAbbgZpwP/dDx/dRb/B9Vjl1sCm/B+2TTU81E+7ce/qijMlEaCTff3oUD19fCYxrF6/oVcEYY8RNryWRckjpsZR/AjXcSUvDJEclL0RaGC0yR05dAtzp4Ny2q5BU+HaPY3myS2V0o0FkyKeE8k2hYVWC5ndxlGgSro=; X-UUID: 3bf25b47e65d41b185baced8352ecaf0-20200812 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 2054378827; Wed, 12 Aug 2020 21:02:35 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Aug 2020 21:02:32 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Aug 2020 21:02:32 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , Philipp Zabel , , , , , , , , Wenbin Mei Subject: [v2,2/3] arm64: dts: mt7622: add reset node for mmc device Date: Wed, 12 Aug 2020 21:01:28 +0800 Message-ID: <20200812130129.13519-3-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200812130129.13519-1-wenbin.mei@mediatek.com> References: <20200812130129.13519-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This commit adds reset node for mmc device. Fixes: 966580ad236e ("mmc: mediatek: add support for MT7622 SoC") Signed-off-by: Wenbin Mei Tested-by: Frank Wunderlich --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 1a39e0ef776b..5b9ec032ce8d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -686,6 +686,8 @@ clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, <&topckgen CLK_TOP_MSDC50_0_SEL>; clock-names = "source", "hclk"; + resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>; + reset-names = "hrst"; status = "disabled"; };