From patchwork Wed Aug 12 13:01:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 11710777 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DFD7C13B6 for ; Wed, 12 Aug 2020 13:02:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7E7620774 for ; Wed, 12 Aug 2020 13:02:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="mGTIkWRs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728018AbgHLNCm (ORCPT ); Wed, 12 Aug 2020 09:02:42 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:4486 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727993AbgHLNCk (ORCPT ); Wed, 12 Aug 2020 09:02:40 -0400 X-UUID: 8b45364098d8405b8e7204291d8662b9-20200812 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CBjDMfS4ZVhji0R5jmv55ojWlHfMqOgeKR+VafpiBXg=; b=mGTIkWRs28RZe81Aqxvi441JCi8aarHLLaBEiNkAVjlC/5VK6nDZhKnuK9uXQ7I/Jcf5cixUhZ04J8uvCx/rRnYKONK6PM5Uw2Ry2Ks4h8Vnt7L8PTJk/kSq9Bx9aG9sldBqsfEF4dcgYaPTi2NzwttRHxSAtSdEm3a7VeqApqk=; X-UUID: 8b45364098d8405b8e7204291d8662b9-20200812 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 303957295; Wed, 12 Aug 2020 21:02:36 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Aug 2020 21:02:33 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Aug 2020 21:02:32 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , Philipp Zabel , , , , , , , , Wenbin Mei Subject: [v2,3/3] mmc: mediatek: add optional module reset property Date: Wed, 12 Aug 2020 21:01:29 +0800 Message-ID: <20200812130129.13519-4-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200812130129.13519-1-wenbin.mei@mediatek.com> References: <20200812130129.13519-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This patch fixs eMMC-Access on mt7622/Bpi-64. Before we got these Errors on mounting eMMC ion R64: [ 48.664925] blk_update_request: I/O error, dev mmcblk0, sector 204800 op 0x1:(WRITE) flags 0x800 phys_seg 1 prio class 0 [ 48.676019] Buffer I/O error on dev mmcblk0p1, logical block 0, lost sync page write This patch adds a optional reset management for msdc. Sometimes the bootloader does not bring msdc register to default state, so need reset the msdc controller. Fixes: 966580ad236e ("mmc: mediatek: add support for MT7622 SoC") Signed-off-by: Wenbin Mei Tested-by: Frank Wunderlich --- drivers/mmc/host/mtk-sd.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 39e7fc54c438..2b243c03c9b2 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -434,6 +435,7 @@ struct msdc_host { struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + struct reset_control *reset; }; static const struct mtk_mmc_compatible mt8135_compat = { @@ -1516,6 +1518,12 @@ static void msdc_init_hw(struct msdc_host *host) u32 val; u32 tune_reg = host->dev_comp->pad_tune_reg; + if (!IS_ERR(host->reset)) { + reset_control_assert(host->reset); + usleep_range(10, 50); + reset_control_deassert(host->reset); + } + /* Configure to MMC/SD mode, clock free running */ sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); @@ -2273,6 +2281,11 @@ static int msdc_drv_probe(struct platform_device *pdev) if (IS_ERR(host->src_clk_cg)) host->src_clk_cg = NULL; + host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, + "hrst"); + if (PTR_ERR(host->reset) == -EPROBE_DEFER) + return PTR_ERR(host->reset); + host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { ret = -EINVAL;