From patchwork Tue Sep 15 06:11:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 11775647 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93C196CA for ; Tue, 15 Sep 2020 06:14:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6EDC6206B2 for ; Tue, 15 Sep 2020 06:14:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Dl1+pVDA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726228AbgIOGNn (ORCPT ); Tue, 15 Sep 2020 02:13:43 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:44321 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726197AbgIOGNY (ORCPT ); Tue, 15 Sep 2020 02:13:24 -0400 X-UUID: 2c88b2d0c0a343d0a363eeceeb207d1a-20200915 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=iHk/Tb8hmYsRyxGTjsN+iuA08DZBLpkgjndj3Jtnz5o=; b=Dl1+pVDAF0qAv0GimU5TaPG9A8HBzxoKtNUSfS13aXxpYGsi8r1HngPiS4fPVbYr9MY61O7hZlaU2S9sAdi2ZGkL7najwMrac34LO6fKDwNOBX7w0gs23tSD0NuIbBOsXAVP13YrzsiKtbH/1v7OX63P4kPfsgL7vGsoXSOX3gY=; X-UUID: 2c88b2d0c0a343d0a363eeceeb207d1a-20200915 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2037843499; Tue, 15 Sep 2020 14:13:22 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Sep 2020 14:13:19 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Sep 2020 14:13:19 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , , , , , , , Wenbin Mei Subject: [RESEND 1/3] mmc: dt-bindings: add support for MT8192 SoC Date: Tue, 15 Sep 2020 14:11:08 +0800 Message-ID: <20200915061110.25833-2-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200915061110.25833-1-wenbin.mei@mediatek.com> References: <20200915061110.25833-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org MT8192 mmc host ip is compatible with MT8183. Add support for this. Signed-off-by: Wenbin Mei --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 26a8f320a156..6422ad7d439d 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -10,7 +10,7 @@ Required properties: - compatible: value should be either of the following. "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 - "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183 + "mediatek,mt8192-mmc", "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516 "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 @@ -27,6 +27,10 @@ Required properties: "hclk" - HCLK which used for host (required) "source_cg" - independent source clock gate (required for MT2712) "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3) + "sys_cg" - msdc subsys clock gate (required for MT8192) + "pclk_cg" - peripheral bus clock gate (required for MT8192) + "axi_cg" - AXI bus clock gate (required for MT8192) + "ahb_cg" - AHB bus clock gate (required for MT8192) - pinctrl-names: should be "default", "state_uhs" - pinctrl-0: should contain default/high speed pin ctrl - pinctrl-1: should contain uhs mode pin ctrl