From patchwork Mon Sep 28 13:09:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 11803775 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B6F2618 for ; Mon, 28 Sep 2020 13:12:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F9E221D95 for ; Mon, 28 Sep 2020 13:12:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="HvKeEfGO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726477AbgI1NMH (ORCPT ); Mon, 28 Sep 2020 09:12:07 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:58431 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726406AbgI1NMH (ORCPT ); Mon, 28 Sep 2020 09:12:07 -0400 X-UUID: cc9ed33b293a4a838e9619e13d966e25-20200928 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DtzmUqahNr9vlnFcH4gqWuTWGefpuIcJc/bsggr42oY=; b=HvKeEfGOz1iBh+8MqCmHBCX4FKeEF9yAl+Vv9xh4MNbQ/5kcXRjuUqOFRSJZIt5+uh9+wnbxfeb07nMhEyeYvKEhfB4s0AHXWNHdRRXILjzsYt5wAHE8WPwcbLoqWXVFJUzN5ZvyUspmbXN3YsoWUGMl5/gqfLLRQkE8CL8Ryyg=; X-UUID: cc9ed33b293a4a838e9619e13d966e25-20200928 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2016316891; Mon, 28 Sep 2020 21:12:01 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Sep 2020 21:11:59 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Sep 2020 21:11:59 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , , , , , , , Wenbin Mei Subject: [PATCH v2 2/4] mmc: dt-bindings: add support for MT8192 SoC Date: Mon, 28 Sep 2020 21:09:16 +0800 Message-ID: <20200928130918.32326-3-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200928130918.32326-1-wenbin.mei@mediatek.com> References: <20200928130918.32326-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org MT8192 mmc host ip is compatible with MT8183. Add support for this. Signed-off-by: Wenbin Mei Reviewed-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 2d5ab1411cd5..f12a44f3e6c4 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -18,6 +18,9 @@ properties: - const: mediatek,mt8135-mmc - const: mediatek,mt8173-mmc - const: mediatek,mt8183-mmc + - items: + - const: mediatek,mt8192-mmc + - const: mediatek,mt8183-mmc - const: mediatek,mt8516-mmc - const: mediatek,mt6779-mmc - const: mediatek,mt2701-mmc @@ -43,21 +46,29 @@ properties: description: Should contain phandle for the clock feeding the MMC controller. minItems: 2 - maxItems: 4 + maxItems: 8 items: - description: source clock (required). - description: HCLK which used for host (required). - description: independent source clock gate (required for MT2712). - description: bus clock used for internal register access (required for MT2712 MSDC0/3). + - description: msdc subsys clock gate (required for MT8192). + - description: peripheral bus clock gate (required for MT8192). + - description: AXI bus clock gate (required for MT8192). + - description: AHB bus clock gate (required for MT8192). clock-names: minItems: 2 - maxItems: 4 + maxItems: 8 items: - const: source - const: hclk - const: source_cg - const: bus_clk + - const: sys_cg + - const: pclk_cg + - const: axi_cg + - const: ahb_cg pinctrl-names: items: