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dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4966.eurprd04.prod.outlook.com (2603:10a6:20b:2::14) by AM6PR04MB5206.eurprd04.prod.outlook.com (2603:10a6:20b:12::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.22; Thu, 26 Nov 2020 11:17:03 +0000 Received: from AM6PR04MB4966.eurprd04.prod.outlook.com ([fe80::3cfc:a92e:75ad:ce4a]) by AM6PR04MB4966.eurprd04.prod.outlook.com ([fe80::3cfc:a92e:75ad:ce4a%3]) with mapi id 15.20.3611.025; Thu, 26 Nov 2020 11:17:03 +0000 From: Dong Aisheng To: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-mmc@vger.kernel.org, Dong Aisheng , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [PATCH RESEND v4 15/18] arm64: dts: imx8qm: add dma ss support Date: Thu, 26 Nov 2020 18:58:57 +0800 Message-Id: <20201126105900.26658-16-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20201126105900.26658-1-aisheng.dong@nxp.com> References: <20201126105900.26658-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0160.apcprd03.prod.outlook.com (2603:1096:4:c9::15) To AM6PR04MB4966.eurprd04.prod.outlook.com (2603:10a6:20b:2::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from b29396-OptiPlex-7040.ap.freescale.net (119.31.174.66) by SG2PR03CA0160.apcprd03.prod.outlook.com (2603:1096:4:c9::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3632.7 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: VzqgNZYuctgctNzzMQOxFItGA0ylcrthGQtm+zFd7D1uYK+C6QFt6SYV31/i3yd8WNbF8893fnwbAcPGcedE06RDN2s3RcxRdYTbUVk20nlcWUF0cgAHK7B4XhFhzxzVPkvxxfFzqKn7g2bxtPMzJqJB5aKmMn+kXWoGyx+vmTWbevt7DzUMNvpHmZVqIiETiBzXvZEZvj+MWLrMYeB7fJSfU83p/T9D03PH0zq+VOYZnP+/B2UPf8x1/QXCul5e4g/nLOFmEMR6SrsosiXZWSXbchBAoPr3kXNB7rEv2yQcGMM+iQ4N0Qrr1aylwC94IyCH8BETwfnrAj5PYAjnnStfJ1CB+ig6w9+K6zk5bdAuv78VYJL6q9CXC2zNG4xm0ZQ1RtA1vZ2VkvKGf8IE8CYZJsxthHVe29HbFwlFxt+m+zGz8WnxI7GqqiroOu3Tt3uEI8EiMnOGKVC33gUj+rrCAPjzRN1DtYXBzDp/eMcQmN/apu25RLDc4D3Tz4U4XhRYGzakjTdyKLOhaQEzViodN9mXy4b6xHqtvex5p2kyivoCpNY0ITEtRa0YpTSJTu9XAlx89WEjQWnDI0pX1arY3jri9Rq8sN34OGWanw5anPPi1e/DDW6vqiEIii4knHQuQARI43h/7YIJj6/7hqlpA+JAJEErhsXd4QSQblu9pfZEribsQe5n0rrZQ1SD+3D9z1IVYk28s4Mdi/hRLOscAfLxjb0EHckD8Rjq7W7HOo16f2KXC4/hmqmk31HvuOia2Bo9TuEnVgGBI5OVspxIpoLwrI63Hf/KXM2Odi5GG3Bxo41+/PTmo3oMS5rmxVUUcd229VvETMpaSsw5Bb2OBpgO60YS1sK81i7MjWTsBbNtm8rWik48mKtamZ1g7mRTqQbakwrNELOFyqppHQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9694f9c4-60ab-4f6d-b8aa-08d891fcccee X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4966.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2020 11:17:03.1026 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vZErEP5Knro2/wtRVZz2DOBGxP+2btNOmUgieuWUpt+RVG5uTOmB51/v3Zi05NiNkZTOXy2/FwszYCb6uq/RSA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5206 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The DMA SS of MX8QM is mostly the same as the DMA part in MX8QXP ADMA SS while it has one more instance for each of LPUART, ADC and LPI2C. And unlike MX8QXP that flexcan clocks are shared between multiple CAN instances, MX8QM has separate flexcan clock slice. So we reuse the most part of common imx8-ss-dma.dtsi and add new things based on it. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- ChangeLog: v2->v3: * use new clock-indices IDs * update lpuart fallback compatible string to fsl,imx8qxp-lpuart v1->v2: * change to the new two cell scu clk binding --- .../boot/dts/freescale/imx8qm-ss-dma.dtsi | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi new file mode 100644 index 000000000000..bbe5f5ecfb92 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +&dma_subsys { + uart4_lpcg: clock-controller@5a4a0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a4a0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "uart4_lpcg_baud_clk", + "uart4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_4>; + }; +}; + +&lpuart0 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&lpuart1 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&lpuart2 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&lpuart3 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&i2c0 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c2 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c3 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +};