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X-MS-Exchange-AntiSpam-MessageData: taTFUYdv9cEQYN0mt/WDnd9ajONVKrV6r8lFmQkQewCkyw14O/2AaGQpjjoaQSlXKzTu2AKqJIlYXxQoxxMR+Ewil2PxAZMCMuoscjtgMpFaM7R8akgIsyddHBil/k/N0QJymwExrZiSqpFEYHlD4VfmRgyIWY6PniedFooProJCDrp7BLkwk+51/wBP0PRrWV8OHO8wv3p+E5HPxOSO41T1s1xm7X7twdz/T/VFgFlyvLsYavfo1XRaJXrrMCWSUW5qB+MMCQXiRnTNOa5zkKhnxrO6DL0hhHoEiZ9xPggllaD+PPi6jWYDHLlERxVc5hZgFYQq4qS4fv10i1QzeAimNwUj9nfg+Zwfk5mFuENgGzCfRIFT4FI9RCQnV8bfmJr6AQLd67+CTdY09DGW/eofwbWLGz2xgH6sVzJYYo5tUXnojlNz8brsYLwZGgtowo8kb172AHE7CjBYrS5Oh9DGo2BKb9xV2m95aZXq0qe4CTW+JkybWTrCUfreYlD4/YWqvWCQa5t+sJJ8+UheK6WXkGRQBjgX22VOlGE3icj+DJyXeiYcnnEgneMPY41aeyxzTNBi46ku5qehVzhdxDU1Jg7N2UYfCwqp2H5RCmpU4wliyNhhtJechgg1f+JeifZ0Ulk7oExUlqIGCSoJWyFHHp7+ywz0x4lZZrBZ2PiyG5ElAcBM9L7BADpYievrNfAgU6kjjVzxGoBdeK8EEzzaGT/nPXmGlU0FnSj+thP1c2byC1+PzbfuusMhQqNBN7FVz1NGPXsKpEbvGpLn9Q/DnIgf2LaDRLbl02WUao/fHIIXg4daN8mntfiTkytKgrztpPJi5OOan7VG0yNvxBzk091mzNOC3L5TjyOoigopHNv0LXc8CgKWd0MT2DNFsVyLQ6TI5x658N5y66lNmQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e592f56-06b6-4459-947d-08d891fcceef X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4966.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2020 11:17:06.4637 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GrAHQ/xkLe2179e0jO0TMWwP6JEv0rXA3D5AnH/rBdSoj/v/eT3T3+tuf2r8Gz41edIClHxrsran4YHea7xPiw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5206 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53 proccessor with powerful graphic and multimedia features. It uses the same architecture as MX8QXP, so many SS can be reused. This patch adds i.MX8QuadMax SoC dtsi file. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- ChangeLog: v3->v4: * change to a new supported scu mu binding v2->v3: * remove a typo change on imx8qxp.dtsi which is unrelated to this patch * include new imx8-lpcg.h v1->v2: * change to the new two cell scu clk binding --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 176 ++++++++++++++++++++++ 1 file changed, 176 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi new file mode 100644 index 000000000000..12cd059b339b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &lpuart0; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&A72_0>; + }; + core1 { + cpu = <&A72_1>; + }; + }; + }; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A72_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + }; + + A72_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + + A72_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x52000000 0 0x2000>, /* GICC */ + <0x0 0x52010000 0 0x1000>, /* GICH */ + <0x0 0x52020000 0 0x20000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", + "rx0", + "gip3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 1 0 + &lsio_mu1 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + + }; + + /* sorted in register address */ + #include "imx8-ss-dma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-lsio.dtsi" +}; + +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-lsio.dtsi"