diff mbox series

[v3,2/2] dt-bindings: mmc: renesas,sdhi: Document RZ/G2L bindings

Message ID 20210804161325.26996-3-biju.das.jz@bp.renesas.com (mailing list archive)
State New, archived
Headers show
Series Document RZ/G2L SDHI controller bindings. | expand

Commit Message

Biju Das Aug. 4, 2021, 4:13 p.m. UTC 
Document RZ/G2L SDHI controller bindings.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3:
 * This patch depends up on the previous patch in this series.
v1->v2:
 * Fixed dtbs-check issue for RZ/A{1,2} platforms.
---
 .../devicetree/bindings/mmc/renesas,sdhi.yaml | 54 +++++++++++++------
 1 file changed, 37 insertions(+), 17 deletions(-)

Comments

Rob Herring Aug. 13, 2021, 5:41 p.m. UTC | #1 
On Wed, Aug 04, 2021 at 05:13:25PM +0100, Biju Das wrote:
> Document RZ/G2L SDHI controller bindings.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
>  * This patch depends up on the previous patch in this series.
> v1->v2:
>  * Fixed dtbs-check issue for RZ/A{1,2} platforms.
> ---
>  .../devicetree/bindings/mmc/renesas,sdhi.yaml | 54 +++++++++++++------
>  1 file changed, 37 insertions(+), 17 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> index 543eeb825dc3..e195ee5c0900 100644
> --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> @@ -44,19 +44,20 @@ properties:
>            - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
>        - items:
>            - enum:
> -              - renesas,sdhi-r8a774a1 # RZ/G2M
> -              - renesas,sdhi-r8a774b1 # RZ/G2N
> -              - renesas,sdhi-r8a774c0 # RZ/G2E
> -              - renesas,sdhi-r8a774e1 # RZ/G2H
> -              - renesas,sdhi-r8a7795  # R-Car H3
> -              - renesas,sdhi-r8a7796  # R-Car M3-W
> -              - renesas,sdhi-r8a77961 # R-Car M3-W+
> -              - renesas,sdhi-r8a77965 # R-Car M3-N
> -              - renesas,sdhi-r8a77970 # R-Car V3M
> -              - renesas,sdhi-r8a77980 # R-Car V3H
> -              - renesas,sdhi-r8a77990 # R-Car E3
> -              - renesas,sdhi-r8a77995 # R-Car D3
> -              - renesas,sdhi-r8a779a0 # R-Car V3U
> +              - renesas,sdhi-r8a774a1  # RZ/G2M
> +              - renesas,sdhi-r8a774b1  # RZ/G2N
> +              - renesas,sdhi-r8a774c0  # RZ/G2E
> +              - renesas,sdhi-r8a774e1  # RZ/G2H
> +              - renesas,sdhi-r8a7795   # R-Car H3
> +              - renesas,sdhi-r8a7796   # R-Car M3-W
> +              - renesas,sdhi-r8a77961  # R-Car M3-W+
> +              - renesas,sdhi-r8a77965  # R-Car M3-N
> +              - renesas,sdhi-r8a77970  # R-Car V3M
> +              - renesas,sdhi-r8a77980  # R-Car V3H
> +              - renesas,sdhi-r8a77990  # R-Car E3
> +              - renesas,sdhi-r8a77995  # R-Car D3
> +              - renesas,sdhi-r8a779a0  # R-Car V3U
> +              - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
>            - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
>  
>    reg:
> @@ -68,13 +69,11 @@ properties:
>  
>    clocks:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 4
>  
>    clock-names:
>      minItems: 1
> -    items:
> -      - const: core
> -      - const: cd
> +    maxItems: 4

The names need to be defined.

>  
>    dmas:
>      minItems: 4
> @@ -135,6 +134,8 @@ allOf:
>                - renesas,sdhi-r7s9210
>      then:
>        properties:
> +        clocks:
> +          maxItems: 2
>          clock-names:
>            items:
>              - const: core
> @@ -146,6 +147,25 @@ allOf:
>          sectioned off to be run by a separate second clock source to allow
>          the main core clock to be turned off to save power.
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,sdhi-r9a07g044
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: IMCLK, SDHI channel main clock1.
> +            - description: IMCLK2, SDHI channel main clock2. When this clock is
> +                           turned off, external SD card detection cannot be
> +                           detected.
> +            - description: CLK_HS, SDHI channel High speed clock which operates
> +                           4 times that of SDHI channel main clock1.
> +            - description: ACLK, SDHI channel bus clock.
> +      required:
> +        - resets
> +
>  required:
>    - compatible
>    - reg
> -- 
> 2.17.1
> 
>
Biju Das Aug. 13, 2021, 6:10 p.m. UTC | #2 
Hi Rob,

Thanks for the feedback.

> Subject: Re: [PATCH v3 2/2] dt-bindings: mmc: renesas,sdhi: Document
> RZ/G2L bindings
> 
> On Wed, Aug 04, 2021 at 05:13:25PM +0100, Biju Das wrote:
> > Document RZ/G2L SDHI controller bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3:
> >  * This patch depends up on the previous patch in this series.
> > v1->v2:
> >  * Fixed dtbs-check issue for RZ/A{1,2} platforms.
> > ---
> >  .../devicetree/bindings/mmc/renesas,sdhi.yaml | 54 +++++++++++++------
> >  1 file changed, 37 insertions(+), 17 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> > index 543eeb825dc3..e195ee5c0900 100644
> > --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> > @@ -44,19 +44,20 @@ properties:
> >            - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
> >        - items:
> >            - enum:
> > -              - renesas,sdhi-r8a774a1 # RZ/G2M
> > -              - renesas,sdhi-r8a774b1 # RZ/G2N
> > -              - renesas,sdhi-r8a774c0 # RZ/G2E
> > -              - renesas,sdhi-r8a774e1 # RZ/G2H
> > -              - renesas,sdhi-r8a7795  # R-Car H3
> > -              - renesas,sdhi-r8a7796  # R-Car M3-W
> > -              - renesas,sdhi-r8a77961 # R-Car M3-W+
> > -              - renesas,sdhi-r8a77965 # R-Car M3-N
> > -              - renesas,sdhi-r8a77970 # R-Car V3M
> > -              - renesas,sdhi-r8a77980 # R-Car V3H
> > -              - renesas,sdhi-r8a77990 # R-Car E3
> > -              - renesas,sdhi-r8a77995 # R-Car D3
> > -              - renesas,sdhi-r8a779a0 # R-Car V3U
> > +              - renesas,sdhi-r8a774a1  # RZ/G2M
> > +              - renesas,sdhi-r8a774b1  # RZ/G2N
> > +              - renesas,sdhi-r8a774c0  # RZ/G2E
> > +              - renesas,sdhi-r8a774e1  # RZ/G2H
> > +              - renesas,sdhi-r8a7795   # R-Car H3
> > +              - renesas,sdhi-r8a7796   # R-Car M3-W
> > +              - renesas,sdhi-r8a77961  # R-Car M3-W+
> > +              - renesas,sdhi-r8a77965  # R-Car M3-N
> > +              - renesas,sdhi-r8a77970  # R-Car V3M
> > +              - renesas,sdhi-r8a77980  # R-Car V3H
> > +              - renesas,sdhi-r8a77990  # R-Car E3
> > +              - renesas,sdhi-r8a77995  # R-Car D3
> > +              - renesas,sdhi-r8a779a0  # R-Car V3U
> > +              - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
> >            - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
> >
> >    reg:
> > @@ -68,13 +69,11 @@ properties:
> >
> >    clocks:
> >      minItems: 1
> > -    maxItems: 2
> > +    maxItems: 4
> >
> >    clock-names:
> >      minItems: 1
> > -    items:
> > -      - const: core
> > -      - const: cd
> > +    maxItems: 4
> 
> The names need to be defined.

Will do. Here we have 3 cases, single clock-name for majority of SoC's,  Two clock-names for sdhi-r7s9210 ("core" and "cd")
and 4 clock names for sdhi-r9a07g044 ("mainclk1", "mainclk2", "hsclk" and "busclk")

Cheers,
Biju

> 
> >
> >    dmas:
> >      minItems: 4
> > @@ -135,6 +134,8 @@ allOf:
> >                - renesas,sdhi-r7s9210
> >      then:
> >        properties:
> > +        clocks:
> > +          maxItems: 2
> >          clock-names:
> >            items:
> >              - const: core
> > @@ -146,6 +147,25 @@ allOf:
> >          sectioned off to be run by a separate second clock source to
> allow
> >          the main core clock to be turned off to save power.
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,sdhi-r9a07g044
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: IMCLK, SDHI channel main clock1.
> > +            - description: IMCLK2, SDHI channel main clock2. When this
> clock is
> > +                           turned off, external SD card detection
> cannot be
> > +                           detected.
> > +            - description: CLK_HS, SDHI channel High speed clock which
> operates
> > +                           4 times that of SDHI channel main clock1.
> > +            - description: ACLK, SDHI channel bus clock.
> > +      required:
> > +        - resets
> > +
> >  required:
> >    - compatible
> >    - reg
> > --
> > 2.17.1
> >
> >
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 543eeb825dc3..e195ee5c0900 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -44,19 +44,20 @@  properties:
           - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
       - items:
           - enum:
-              - renesas,sdhi-r8a774a1 # RZ/G2M
-              - renesas,sdhi-r8a774b1 # RZ/G2N
-              - renesas,sdhi-r8a774c0 # RZ/G2E
-              - renesas,sdhi-r8a774e1 # RZ/G2H
-              - renesas,sdhi-r8a7795  # R-Car H3
-              - renesas,sdhi-r8a7796  # R-Car M3-W
-              - renesas,sdhi-r8a77961 # R-Car M3-W+
-              - renesas,sdhi-r8a77965 # R-Car M3-N
-              - renesas,sdhi-r8a77970 # R-Car V3M
-              - renesas,sdhi-r8a77980 # R-Car V3H
-              - renesas,sdhi-r8a77990 # R-Car E3
-              - renesas,sdhi-r8a77995 # R-Car D3
-              - renesas,sdhi-r8a779a0 # R-Car V3U
+              - renesas,sdhi-r8a774a1  # RZ/G2M
+              - renesas,sdhi-r8a774b1  # RZ/G2N
+              - renesas,sdhi-r8a774c0  # RZ/G2E
+              - renesas,sdhi-r8a774e1  # RZ/G2H
+              - renesas,sdhi-r8a7795   # R-Car H3
+              - renesas,sdhi-r8a7796   # R-Car M3-W
+              - renesas,sdhi-r8a77961  # R-Car M3-W+
+              - renesas,sdhi-r8a77965  # R-Car M3-N
+              - renesas,sdhi-r8a77970  # R-Car V3M
+              - renesas,sdhi-r8a77980  # R-Car V3H
+              - renesas,sdhi-r8a77990  # R-Car E3
+              - renesas,sdhi-r8a77995  # R-Car D3
+              - renesas,sdhi-r8a779a0  # R-Car V3U
+              - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
           - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
 
   reg:
@@ -68,13 +69,11 @@  properties:
 
   clocks:
     minItems: 1
-    maxItems: 2
+    maxItems: 4
 
   clock-names:
     minItems: 1
-    items:
-      - const: core
-      - const: cd
+    maxItems: 4
 
   dmas:
     minItems: 4
@@ -135,6 +134,8 @@  allOf:
               - renesas,sdhi-r7s9210
     then:
       properties:
+        clocks:
+          maxItems: 2
         clock-names:
           items:
             - const: core
@@ -146,6 +147,25 @@  allOf:
         sectioned off to be run by a separate second clock source to allow
         the main core clock to be turned off to save power.
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,sdhi-r9a07g044
+    then:
+      properties:
+        clocks:
+          items:
+            - description: IMCLK, SDHI channel main clock1.
+            - description: IMCLK2, SDHI channel main clock2. When this clock is
+                           turned off, external SD card detection cannot be
+                           detected.
+            - description: CLK_HS, SDHI channel High speed clock which operates
+                           4 times that of SDHI channel main clock1.
+            - description: ACLK, SDHI channel bus clock.
+      required:
+        - resets
+
 required:
   - compatible
   - reg