| Message ID | 20220711082940.39539-4-krzysztof.kozlowski@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dt-bindings: mmc: / ARM: qcom: correct reg-names and clock entries | expand |
On 11.07.2022 10:29, Krzysztof Kozlowski wrote: > DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, > just like TXT bindings were expecting before the conversion. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: Douglas Anderson <dianders@chromium.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/msm8953.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- > 6 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > index a6cb0dafcc17..2b9374f61d5b 100644 > --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > @@ -379,7 +379,7 @@ spmi_bus: spmi@200f000 { > sdhc_1: mmc@7824900 { > compatible = "qcom,sdhci-msm-v4"; > reg = <0x7824900 0x500>, <0x7824000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 48bc2e09128d..0bdf4d39f778 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -1469,7 +1469,7 @@ lpass_codec: audio-codec@771c000 { > sdhc_1: mmc@7824000 { > compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; > reg = <0x07824900 0x11c>, <0x07824000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > @@ -1487,7 +1487,7 @@ sdhc_1: mmc@7824000 { > sdhc_2: mmc@7864000 { > compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; > reg = <0x07864900 0x11c>, <0x07864000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi > index 1bc0ef476cdb..97dde1a429d9 100644 > --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi > @@ -799,7 +799,7 @@ sdhc_1: mmc@7824900 { > compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; > > reg = <0x7824900 0x500>, <0x7824000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > @@ -859,7 +859,7 @@ sdhc_2: mmc@7864900 { > compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; > > reg = <0x7864900 0x500>, <0x7864000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi > index 8bc6c070e306..35c1ca080684 100644 > --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi > @@ -464,7 +464,7 @@ usb@f9200000 { > sdhc1: mmc@f9824900 { > compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; > reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > @@ -487,7 +487,7 @@ sdhc1: mmc@f9824900 { > sdhc2: mmc@f98a4900 { > compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; > reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index 25d6b26fab60..9745df5dc007 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -2896,7 +2896,7 @@ hsusb_phy2: phy@7412000 { > sdhc1: mmc@7464900 { > compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; > reg = <0x07464900 0x11c>, <0x07464000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; > @@ -2920,7 +2920,7 @@ sdhc1: mmc@7464900 { > sdhc2: mmc@74a4900 { > compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; > reg = <0x074a4900 0x314>, <0x074a4000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi > index e263a59d84b0..c98f36f95f3c 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi > @@ -2078,7 +2078,7 @@ qusb2phy: phy@c012000 { > sdhc2: mmc@c0a4900 { > compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; > reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; > - reg-names = "hc_mem", "core_mem"; > + reg-names = "hc", "core"; > > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index a6cb0dafcc17..2b9374f61d5b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -379,7 +379,7 @@ spmi_bus: spmi@200f000 { sdhc_1: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 48bc2e09128d..0bdf4d39f778 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1469,7 +1469,7 @@ lpass_codec: audio-codec@771c000 { sdhc_1: mmc@7824000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -1487,7 +1487,7 @@ sdhc_1: mmc@7824000 { sdhc_2: mmc@7864000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 1bc0ef476cdb..97dde1a429d9 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -799,7 +799,7 @@ sdhc_1: mmc@7824900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -859,7 +859,7 @@ sdhc_2: mmc@7864900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7864900 0x500>, <0x7864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 8bc6c070e306..35c1ca080684 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -464,7 +464,7 @@ usb@f9200000 { sdhc1: mmc@f9824900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -487,7 +487,7 @@ sdhc1: mmc@f9824900 { sdhc2: mmc@f98a4900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 25d6b26fab60..9745df5dc007 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2896,7 +2896,7 @@ hsusb_phy2: phy@7412000 { sdhc1: mmc@7464900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07464900 0x11c>, <0x07464000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; @@ -2920,7 +2920,7 @@ sdhc1: mmc@7464900 { sdhc2: mmc@74a4900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index e263a59d84b0..c98f36f95f3c 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2078,7 +2078,7 @@ qusb2phy: phy@c012000 { sdhc2: mmc@c0a4900 { compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;