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Fri, 10 Nov 2023 02:11:06 -0600 From: Sai Krishna Potthuri To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek , Adrian Hunter CC: , , , , Subject: [PATCH] dt bindings: mmc: arasan,sdci: Add gate property for Xilinx platforms Date: Fri, 10 Nov 2023 13:41:05 +0530 Message-ID: <20231110081105.3295037-1-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003442:EE_|DS0PR12MB7583:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e9f3157-0a03-444a-842b-08dbe1c498fd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MZcibu/kNGTH+PVBI4btOVP4Q/rsm4mCUOMUyGBGrFJyUaPhI3G910UeUR7d9yBtqgKJ42E4ONt7/5hOx+S9IHSoXQXBIaEgSrLZTby4WB1H87OxzLRK9ljtLVfJInRe3Q+VdM+VOzRe8AtL0YZ0MaLjWg8u0TncushRD9baOhyZvUJbOT7Bo1DpvxJbow52XA0HqV6dRDfXmPc93xMyGjyL+yfFu5sXMI9gVg6bK6zmHQPvWUj04mrAC1bZxMNjjH8yZfB2LbuoSr9K7l8Gtj7dTMMkr0dyiwk1iGj5PdV3EZyYGyzMwKsje6j0H9hF1oKrNXFVCqeu07mJ5g03MlHX0A73qzOQNECG1Fi2q7Ch11Dd9sMKXe3EMqonIh4BZe8Ey5Js+11CN/p1myTQCHMyyrmRc9KgD9BxSn4kyIqjvhBJEixWq5fB3TEhCGeDJMLFJAyerxpjVocXS9kmdGLQDpIbXBVCwYoMaaRFSnwLVaTxUQJvMd7dzsRtgacksbtQA22TwJcRT1sgN6s2a0M9WQAyP6o6sH5Kldm2J3hJ3yYFrqk5UA9e2C6+gX8q31Jx/VQopxt2odqGa08nyMIKy5cK3jiGKEPjuiogE5ZP8n3DM8iS26tk9h4dUsT6CXQYYLRL3txqkl6adXwyOEStfZNTVA7ZTlHVwfI/W//U5Fo+52uY6+hVIhnMBVPug544ZW8Cbu+KQumbjvmfwKb4IYuNDvLrEuL13QmrbT175PrN4U2hFzp4DKfJru1N/5Ao3n73MVTgK7fydWRRnw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(376002)(136003)(39860400002)(230922051799003)(82310400011)(64100799003)(451199024)(1800799009)(186009)(40470700004)(46966006)(36840700001)(40480700001)(40460700003)(47076005)(36860700001)(41300700001)(36756003)(4326008)(8936002)(8676002)(86362001)(103116003)(356005)(478600001)(2906002)(5660300002)(316002)(83380400001)(110136005)(82740400003)(81166007)(70586007)(426003)(70206006)(54906003)(26005)(2616005)(7416002)(336012)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2023 08:11:09.8866 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e9f3157-0a03-444a-842b-08dbe1c498fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003442.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7583 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Swati Agarwal Add gate property in example node for Xilinx platforms which will be used to ungate the DLL clock. DLL clock is required for higher frequencies like 50MHz, 100MHz and 200MHz. DLL clock is automatically selected by the SD controller when the SD output clock frequency is more than 25 MHz. Signed-off-by: Swati Agarwal Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Acked-by: Krzysztof Kozlowski --- Note: This patch only updates the example nodes with the gate property for Xilinx platforms. Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index 3e99801f77d2..9075add020bf 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -226,8 +226,8 @@ examples: interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0xff160000 0x1000>; - clocks = <&clk200>, <&clk200>; - clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk200>, <&clk200>, <&clk1200>; + clock-names = "clk_xin", "clk_ahb", "gate"; clock-output-names = "clk_out_sd0", "clk_in_sd0"; #clock-cells = <1>; clk-phase-sd-hs = <63>, <72>; @@ -239,8 +239,8 @@ examples: interrupt-parent = <&gic>; interrupts = <0 126 4>; reg = <0xf1040000 0x10000>; - clocks = <&clk200>, <&clk200>; - clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk200>, <&clk200>, <&clk1200>; + clock-names = "clk_xin", "clk_ahb", "gate"; clock-output-names = "clk_out_sd0", "clk_in_sd0"; #clock-cells = <1>; clk-phase-sd-hs = <132>, <60>;