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[RFC,V2,09/12] dt-bindings: misc: tegra-sdhci: config settings

Message ID 20240701151231.29425-10-kyarlagadda@nvidia.com (mailing list archive)
State New
Headers show
Series Introduce Tegra register config settings | expand

Commit Message

Krishna Yarlagadda July 1, 2024, 3:12 p.m. UTC 
SDHCI vendor tuning registers are configured using config setting
framework. List available field config for Tegra SDHCI controllers.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 .../misc/nvidia,tegra-config-settings.yaml    | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra-config-settings.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra-config-settings.yaml
index 5f4da633e69b..f4440cb6286d 100644
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra-config-settings.yaml
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra-config-settings.yaml
@@ -38,6 +38,32 @@  patternProperties:
     additionalProperties: false
 
     patternProperties:
+      "^sdhci-[a-z0-9_-]+-cfg$":
+        description: Config settings for SDHCI devices.
+          SDHCI has configuration based on device speed modes.
+          - common is set on all speeds and can be overridden by speed mode.
+          - List of speed modes and their config name
+            "default", /* MMC_TIMING_LEGACY */
+            "sd-mmc-highspeed", /* MMC_TIMING_MMC_HS */
+            "sd-mmc-highspeed", /* MMC_TIMING_SD_HS */
+            "uhs-sdr12", /* MMC_TIMING_UHS_SDR12 */
+            "uhs-sdr25", /* MMC_TIMING_UHS_SDR25 */
+            "uhs-sdr50", /* MMC_TIMING_UHS_SDR50 */
+            "uhs-sdr104", /* MMC_TIMING_UHS_SDR104 */
+            "uhs-ddr52", /* MMC_TIMING_UHS_DDR50 */
+            "uhs-ddr52", /* MMC_TIMING_MMC_DDR52 */
+            "mmc-hs200", /* MMC_TIMING_MMC_HS200 */
+            "mmc-hs400", /* MMC_TIMING_MMC_HS400 */
+        type: object
+        additionalProperties: false
+
+        properties:
+          nvidia,mmc-num-tuning-iter:
+            description: Specify DQS trim value for HS400 timing.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 0
+            maximum: 0xffff
+
       "^i2c-[a-z0-9_]+-cfg$":
         description: Config settings for I2C devices.
         type: object
@@ -124,4 +150,9 @@  examples:
                 nvidia,i2c-sclk-high-period = <0x07>;
             };
         };
+        configmmc1: config-mmc3400000 {
+            sdhci-mmc-hs200-cfg {
+                nvidia,mmc-num-tuning-iter = <0x02>;
+            };
+        };
     };