| Message ID | 20240701151231.29425-11-kyarlagadda@nvidia.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show
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Mon, 1 Jul 2024 08:13:33 -0700 From: Krishna Yarlagadda <kyarlagadda@nvidia.com> To: <linux-tegra@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>, <linux-i2c@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <linux-kernel@vger.kernel.org> CC: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>, <corbet@lwn.net>, <andi.shyti@kernel.org>, <wsa+renesas@sang-engineering.com>, <ulf.hansson@linaro.org>, <adrian.hunter@intel.com>, <digetx@gmail.com>, <ldewangan@nvidia.com>, <kyarlagadda@nvidia.com>, <mkumard@nvidia.com> Subject: [RFC PATCH V2 10/12] dt-bindings: mmc: tegra-sdhci: reference to config Date: Mon, 1 Jul 2024 20:42:28 +0530 Message-ID: <20240701151231.29425-11-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240701151231.29425-1-kyarlagadda@nvidia.com> References: <20240701151231.29425-1-kyarlagadda@nvidia.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: <linux-mmc.vger.kernel.org> List-Subscribe: <mailto:linux-mmc+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-mmc+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE38:EE_|PH7PR12MB7938:EE_ X-MS-Office365-Filtering-Correlation-Id: 08e297bd-0fd1-4561-eaf6-08dc99e06ed5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; 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Introduce Tegra register config settings
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expand
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diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml index 72987f0326a1..39bda6ce1e50 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -88,6 +88,10 @@ properties: items: - description: phandle to the core power domain + config-settings: + description: phandle to the sdhci configuration settings + $ref: /schemas/types.yaml#/definitions/phandle + nvidia,default-tap: description: Specify the default inbound sampling clock trimmer value for non-tunable modes.
SDHCI vendor tuning registers are configured using config setting framework. Add reference to SDHCI controllers config settings. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> --- .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml | 4 ++++ 1 file changed, 4 insertions(+)