From patchwork Fri Dec 3 19:29:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Rakity X-Patchwork-Id: 378791 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB3JXO54025698 for ; Fri, 3 Dec 2010 19:33:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752996Ab0LCTdX (ORCPT ); Fri, 3 Dec 2010 14:33:23 -0500 Received: from na3sys009aog109.obsmtp.com ([74.125.149.201]:60082 "HELO na3sys009aog109.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1752659Ab0LCTdX convert rfc822-to-8bit (ORCPT ); Fri, 3 Dec 2010 14:33:23 -0500 Received: from source ([65.219.4.129]) (using TLSv1) by na3sys009aob109.postini.com ([74.125.148.12]) with SMTP ID DSNKTPlF/gBiw+/lQufNUtuw74pGeC/HKgXB@postini.com; Fri, 03 Dec 2010 11:33:22 PST Received: from SC-vEXCH3.marvell.com ([10.93.76.133]) by SC-OWA01.marvell.com ([10.93.76.21]) with mapi; Fri, 3 Dec 2010 11:29:36 -0800 From: Philip Rakity To: "linux-mmc@vger.kernel.org" CC: Nicolas Pitre , Linus Walleij Date: Fri, 3 Dec 2010 11:29:35 -0800 Subject: [PATCH 3/3 ] mmc: add support for h/w clock gating of sd controller Thread-Topic: [PATCH 3/3 ] mmc: add support for h/w clock gating of sd controller Thread-Index: AcuTIGsoI7IIc0NIQ5C43vl5CCGrxA== Message-ID: <4840F7B2-1DB1-4047-A5F4-F490B712E38D@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 03 Dec 2010 19:33:24 +0000 (UTC) diff --git a/drivers/mmc/host/sdhci-pxa.c b/drivers/mmc/host/sdhci-pxa.c index 5a61208..e2cc851 100644 --- a/drivers/mmc/host/sdhci-pxa.c +++ b/drivers/mmc/host/sdhci-pxa.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "sdhci.h" #define DRIVER_NAME "sdhci-pxa" @@ -46,10 +47,27 @@ struct sdhci_pxa { * SDHCI core callbacks * * * \*****************************************************************************/ +#ifdef CONFIG_MMC_CLKGATE +static void hardware_clk_gating (struct sdhci_host *host) +{ + unsigned short tmp; + int enable; + + enable = host->mmc->clk_gated; + tmp = readw(host->ioaddr + SD_FIFO_PARAM); + + if (enable) + tmp &= ~DIS_PAD_SD_CLK_GATE; + else + tmp |= DIS_PAD_SD_CLK_GATE; + + writew(tmp, host->ioaddr + SD_FIFO_PARAM); +} +#endif + static void set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pxa *pxa = sdhci_priv(host); - u32 tmp = 0; if (clock == 0) { if (pxa->clk_enable) { @@ -58,11 +76,6 @@ static void set_clock(struct sdhci_host *host, unsigned int clock) } } else { if (0 == pxa->clk_enable) { - if (pxa->pdata->flags & PXA_FLAG_DISABLE_CLOCK_GATING) { - tmp = readl(host->ioaddr + SD_FIFO_PARAM); - tmp |= DIS_PAD_SD_CLK_GATE; - writel(tmp, host->ioaddr + SD_FIFO_PARAM); - } clk_enable(pxa->clk); pxa->clk_enable = 1; } @@ -71,6 +84,9 @@ static void set_clock(struct sdhci_host *host, unsigned int clock) static struct sdhci_ops sdhci_pxa_ops = { .set_clock = set_clock, +#ifdef CONFIG_MMC_CLKGATE + .platform_hw_clk_gate = hardware_clk_gating, +#endif }; /*****************************************************************************\ @@ -145,6 +161,11 @@ static int __devinit sdhci_pxa_probe(struct platform_device *pdev) if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) host->mmc->caps |= MMC_CAP_8_BIT_DATA; +#ifdef CONFIG_MMC_CLKGATE + if (cpu_is_mmp2()) + host->mmc->caps |= MMC_CAP_CLOCK_GATING_HW; +#endif + ret = sdhci_add_host(host); if (ret) { dev_err(&pdev->dev, "failed to add host\n");