From patchwork Fri Jan 21 19:26:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Rakity X-Patchwork-Id: 496211 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p0LJOOH9003667 for ; Fri, 21 Jan 2011 19:26:54 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754788Ab1AUT0y (ORCPT ); Fri, 21 Jan 2011 14:26:54 -0500 Received: from na3sys009aog107.obsmtp.com ([74.125.149.197]:54055 "HELO na3sys009aog107.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1753971Ab1AUT0y convert rfc822-to-8bit (ORCPT ); Fri, 21 Jan 2011 14:26:54 -0500 Received: from source ([65.219.4.129]) (using TLSv1) by na3sys009aob107.postini.com ([74.125.148.12]) with SMTP ID DSNKTTnd/QFp/qu9EWnFMKNvaevDSY49aSrF@postini.com; Fri, 21 Jan 2011 11:26:54 PST Received: from SC-vEXCH3.marvell.com ([10.93.76.133]) by SC-OWA01.marvell.com ([10.93.76.21]) with mapi; Fri, 21 Jan 2011 11:26:40 -0800 From: Philip Rakity To: "linux-mmc@vger.kernel.org" CC: Mark Brown Date: Fri, 21 Jan 2011 11:26:40 -0800 Subject: [PATCH] sdhci: Add pre and post reset processing for chip specific reset Thread-Topic: [PATCH] sdhci: Add pre and post reset processing for chip specific reset Thread-Index: Acu5oSEWmrwtW4z6QuKrMunrNPPf2A== Message-ID: <49807409-2DDA-4C6D-AD98-ECDEF8B3B633@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 21 Jan 2011 19:26:55 +0000 (UTC) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index d5febe5..f439881 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -157,6 +157,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) ier = sdhci_readl(host, SDHCI_INT_ENABLE); + if (host->ops->platform_reset_enter) + host->ops->platform_reset_enter(host, mask); + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); if (mask & SDHCI_RESET_ALL) @@ -177,6 +180,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) mdelay(1); } + if (host->ops->platform_reset_exit) + host->ops->platform_reset_exit(host, mask); + if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 6e0969e..9dd7bc1 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -222,6 +222,8 @@ struct sdhci_ops { void (*platform_send_init_74_clocks)(struct sdhci_host *host, u8 power_mode); unsigned int (*get_ro)(struct sdhci_host *host); + void (*platform_reset_enter)(struct sdhci_host *host, u8 mask); + void (*platform_reset_exit)(struct sdhci_host *host, u8 mask); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS