From patchwork Fri Jan 27 21:38:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 9542753 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7DB3F60415 for ; Fri, 27 Jan 2017 21:53:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6FB2A204C1 for ; Fri, 27 Jan 2017 21:53:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 63BD827A98; Fri, 27 Jan 2017 21:53:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 112A1204C1 for ; Fri, 27 Jan 2017 21:53:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751667AbdA0VxY (ORCPT ); Fri, 27 Jan 2017 16:53:24 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:38499 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751897AbdA0Vv7 (ORCPT ); Fri, 27 Jan 2017 16:51:59 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id B73C820DE5; Fri, 27 Jan 2017 22:39:12 +0100 (CET) Received: from localhost (LFbn-1-2281-83.w90-76.abo.wanadoo.fr [90.76.98.83]) by mail.free-electrons.com (Postfix) with ESMTPSA id E6E3720DE9; Fri, 27 Jan 2017 22:38:54 +0100 (CET) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , Ulf Hansson Cc: Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Andre Przywara Subject: [PATCH v5 4/13] mmc: sunxi: Enable the new timings for the A64 MMC controllers Date: Fri, 27 Jan 2017 22:38:36 +0100 Message-Id: <4a2be38120cebd8bed2358b19addb0985fe28a61.1485553113.git-series.maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The A64 MMC controllers need to set a "new timings" bit when a new rate is set. The actual meaning of that bit is not clear yet, but not setting it leads to some corner-case issues, like the CMD53 failing, which is used to implement SDIO packet aggregation. Signed-off-by: Maxime Ripard Tested-by: Florian Vaussard --- drivers/mmc/host/sunxi-mmc.c | 6 ++++++ 1 file changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index b9c8a62bc212..51d6388a194e 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -253,6 +253,8 @@ struct sunxi_mmc_cfg { /* does the IP block support autocalibration? */ bool can_calibrate; + + bool needs_new_timings; }; struct sunxi_mmc_host { @@ -779,6 +781,9 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, } mmc_writel(host, REG_CLKCR, rval); + if (host->cfg->needs_new_timings) + mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE); + ret = sunxi_mmc_clk_set_phase(host, ios, rate); if (ret) return ret; @@ -1076,6 +1081,7 @@ static const struct sunxi_mmc_cfg sun50i_a64_cfg = { .idma_des_size_bits = 16, .clk_delays = NULL, .can_calibrate = true, + .needs_new_timings = true, }; static const struct of_device_id sunxi_mmc_of_match[] = {