From patchwork Tue May 22 06:42:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabu Thangamuthu X-Patchwork-Id: 10417377 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1F0E9600CC for ; Tue, 22 May 2018 06:42:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0CC8428B44 for ; Tue, 22 May 2018 06:42:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0133E28B47; Tue, 22 May 2018 06:42:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D9AB728B44 for ; Tue, 22 May 2018 06:42:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751024AbeEVGmp (ORCPT ); Tue, 22 May 2018 02:42:45 -0400 Received: from smtprelay.synopsys.com ([198.182.37.59]:47920 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750954AbeEVGmo (ORCPT ); Tue, 22 May 2018 02:42:44 -0400 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id 63ABA1E0490; Tue, 22 May 2018 08:42:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1526971362; bh=3PSlBWeoFSwjExdccLE5mR/SS7lkklN+Wjud/QjUPS8=; h=From:To:CC:Subject:Date:From; b=hhUAd0/if/uKKccFAOluDL80AVRSJQG/6JDjzpJ9H+Ths0bsBWBsuOuzhPVcLoZ2j qqQPXI2Xa8awT4Mj5k0WIy0hKcnR5baVowzYT7r84wcnVEg8J+Kgf/1Gmchvo2Y0YD GUKE78OBRDkdiV42qWImO/JRDsjXNw+qvwL29iOTYVg1lh+O7h5EaacjxZWPChguvC NCxBu/SsxFSfqeEsCSPi9hJkJu/3rLjMK7N5MAC+KzclYwqTwOgcEshJvgbolrCgKH LKq38X3xuMnji9GnHvgcVccbVYtDuDjxHG/S19b6BlE1MSAggfN8wRtcB3gePQGNWN 98S7k/dAdbHuQ== Received: from US01WEHTC3.internal.synopsys.com (us01wehtc3.internal.synopsys.com [10.15.84.232]) by mailhost.synopsys.com (Postfix) with ESMTP id B58935B4D; Mon, 21 May 2018 23:42:41 -0700 (PDT) Received: from IN01WEHTCA.internal.synopsys.com (10.144.199.104) by US01WEHTC3.internal.synopsys.com (10.15.84.232) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 21 May 2018 23:42:41 -0700 Received: from IN01WEMBXB.internal.synopsys.com ([169.254.4.157]) by IN01WEHTCA.internal.synopsys.com ([::1]) with mapi id 14.03.0361.001; Tue, 22 May 2018 12:12:39 +0530 From: Prabu Thangamuthu To: "ulf.hansson@linaro.org" , Adrian Hunter , "linux-kernel@vger.kernel.org" , "linux-mmc@vger.kernel.org" CC: Manjunath M Bettegowda , "prabu.t@synopsys.com" Subject: [PATCH 1/1] mmc: sdhci-pci-dwc-mshc: synopsys dwc mshc support Thread-Topic: [PATCH 1/1] mmc: sdhci-pci-dwc-mshc: synopsys dwc mshc support Thread-Index: AdPxmBIFOmCk2CVqRi+baz/mIdVd7Q== Date: Tue, 22 May 2018 06:42:39 +0000 Message-ID: <705D14B1C7978B40A723277C067CEDE2010A9B43CC@IN01WEMBXB.internal.synopsys.com> Accept-Language: en-US, en-IN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.12.239.235] MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To enable Synopsys DWC MSHC controller on HPAS-DX platform connected using PCIe interface. As Clock generation logic is implemented in MMCM module of HAPS-DX platform, we have separate functions to control the MMCM to generate required clocks with respect to speed mode. Also we have platform specific set_power function to support different VDD of eMMC devices. Signed-off-by: Prabu Thangamuthu --- MAINTAINERS | 7 ++ drivers/mmc/host/Makefile | 3 +- drivers/mmc/host/sdhci-pci-core.c | 1 + drivers/mmc/host/sdhci-pci-dwc-mshc.c | 146 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-pci-dwc-mshc.h | 37 +++++++++ drivers/mmc/host/sdhci-pci.h | 3 + 6 files changed, 196 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/host/sdhci-pci-dwc-mshc.c create mode 100644 drivers/mmc/host/sdhci-pci-dwc-mshc.h #endif /* __SDHCI_PCI_H */ diff --git a/MAINTAINERS b/MAINTAINERS index 9051a9c..f1749c4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12643,6 +12643,13 @@ S: Maintained F: drivers/mmc/host/sdhci* F: include/linux/mmc/sdhci* +SYNOPSYS SDHCI COMPLIANT DWC MSHC DRIVER +M: Prabu Thangamuthu +M: Manjunath M B +L: linux-mmc@vger.kernel.org +S: Maintained +F: drivers/mmc/host/sdhci-pci-dwc-mshc* + SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) SAMSUNG DRIVER M: Ben Dooks M: Jaehoon Chung diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 6aead24..6c0d3fb 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -11,7 +11,8 @@ obj-$(CONFIG_MMC_MXC) += mxcmmc.o obj-$(CONFIG_MMC_MXS) += mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o -sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o +sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \ + sdhci-pci-dwc-mshc.o obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index 77dd352..96b6963 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -1511,6 +1511,7 @@ static int amd_probe(struct sdhci_pci_chip *chip) SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), + SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), /* Generic SD host controller */ {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, diff --git a/drivers/mmc/host/sdhci-pci-dwc-mshc.c b/drivers/mmc/host/sdhci-pci-dwc-mshc.c new file mode 100644 index 0000000..bca3db4 --- /dev/null +++ b/drivers/mmc/host/sdhci-pci-dwc-mshc.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDHCI driver for Synopsys DWC_MSHC controller + * + * Copyright (C) 2018 Synopsys, Inc. (www.synopsys.com) + * + * Authors: + * Prabu Thangamuthu + * Manjunath M B + * + */ + +#include +#include +#include +#include + +#include "sdhci.h" +#include "sdhci-pci.h" +#include "sdhci-pci-dwc-mshc.h" + +/* Default emmc vdd is set to 3.3V */ +static unsigned int emmc_vdd = SDHC_EMMC_VDD_330V; +module_param(emmc_vdd, int, 0444); + +static void sdhci_snps_set_clock(struct sdhci_host *host, unsigned int clock) +{ + u16 clk = 0; + u32 reg = 0; + u32 vendor_ptr = 0; + + vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R); + + /* Disable Software managed rx tuning */ + reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); + reg &= ~SDHC_SW_TUNE_EN; + sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr)); + + if (clock <= 52000000) { + sdhci_set_clock(host, clock); + } else { + /* Assert reset to MMCM */ + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); + reg |= SDHC_CCLK_MMCM_RST; + sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); + + /* Configure MMCM*/ + sdhci_writel(host, DIV_REG_100_MHZ, SDHC_MMCM_DIV_REG); + sdhci_writel(host, CLKFBOUT_100_MHZ, + SDHC_MMCM_CLKFBOUT); + + /* De-assert reset to MMCM*/ + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); + reg &= ~SDHC_CCLK_MMCM_RST; + sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); + + /* Enable clock */ + clk = SDHCI_PROG_CLOCK_MODE | SDHCI_CLOCK_INT_EN | + SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + } +} + +static void sdhci_snps_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + u8 pwr = 0; + u16 ctrl; + + if (mode != MMC_POWER_OFF) { + switch (1 << vdd) { + case MMC_VDD_165_195: + pwr = SDHCI_POWER_180; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + pwr = SDHCI_POWER_300; + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + pwr = SDHCI_POWER_330; + break; + default: + WARN(1, "%s: Invalid vdd %#x\n", + mmc_hostname(host->mmc), vdd); + break; + } + } + + if (host->pwr == pwr) + return; + + host->pwr = pwr; + + if (pwr == 0) { + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + } else { + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + /* + * Enable it for eMMC phy cfg1 test with 1.8V mode + */ + if (emmc_vdd == SDHC_EMMC_VDD_180V) { + pwr = SDHCI_POWER_180; + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* + * Enable 1.8V Signal Enable in the Host Control2 + * register + */ + ctrl |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + } + pwr |= SDHCI_POWER_ON; + + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + } +} + +static int sdhci_snps_pci_probe_slot(struct sdhci_pci_slot *slot) +{ + struct sdhci_host *host = slot->host; + + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); + host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); + + return 0; +} + +/* Synopsys DWC MSHC Controller based on SDHCI-PCI */ +static const struct sdhci_ops sdhci_snps_ops = { + .set_clock = sdhci_snps_set_clock, + .set_power = sdhci_snps_set_power, + .enable_dma = sdhci_pci_enable_dma, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + +const struct sdhci_pci_fixes sdhci_snps = { + .probe_slot = sdhci_snps_pci_probe_slot, + .ops = &sdhci_snps_ops, +}; + +MODULE_PARM_DESC(emmc_vdd, "VDD to configure eMMC device supply voltage"); diff --git a/drivers/mmc/host/sdhci-pci-dwc-mshc.h b/drivers/mmc/host/sdhci-pci-dwc-mshc.h new file mode 100644 index 0000000..352bbfd --- /dev/null +++ b/drivers/mmc/host/sdhci-pci-dwc-mshc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SDHCI driver for Synopsys DWC_MSHC controller + * + * Copyright (C) 2018 Synopsys, Inc. (www.synopsys.com) + * + * Authors: + * Prabu Thangamuthu + * Manjunath M B + * + */ + +#ifndef __SDHCI_PCI_DWC_MSHC_H__ +#define __SDHCI_PCI_DWC_MSHC_H__ + +#define SDHCI_VENDOR_PTR_R 0xE8 + +/* Module Parameters */ +#define SDHC_EMMC_VDD_330V 33 +#define SDHC_EMMC_VDD_180V 18 + +/* Synopsys Vendor Specific Registers */ +#define SDHC_GPIO_OUT 0x34 +#define SDHC_AT_CTRL_R 0x40 + +#define SDHC_SW_TUNE_EN 0x00000010 + +/* MMCM DRP */ +#define SDHC_MMCM_DIV_REG 0x1020 +#define DIV_REG_100_MHZ 0x1145 + +#define SDHC_MMCM_CLKFBOUT 0x1024 +#define CLKFBOUT_100_MHZ 0x0000 + +#define SDHC_CCLK_MMCM_RST 0x00000001 + +#endif diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index db9cb54..c91dcec 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -59,6 +59,7 @@ #define PCI_VENDOR_ID_ARASAN 0x16e6 #define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670 +#define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xC202 /* * PCI device class and mask */ @@ -183,4 +184,6 @@ static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) extern const struct sdhci_pci_fixes sdhci_arasan; +extern const struct sdhci_pci_fixes sdhci_snps; +