From patchwork Fri Oct 8 19:31:34 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Rakity X-Patchwork-Id: 242231 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o98JVvDm023622 for ; Fri, 8 Oct 2010 19:31:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759518Ab0JHTbj (ORCPT ); Fri, 8 Oct 2010 15:31:39 -0400 Received: from na3sys009aog111.obsmtp.com ([74.125.149.205]:60244 "HELO na3sys009aog111.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1759493Ab0JHTbh convert rfc822-to-8bit (ORCPT ); Fri, 8 Oct 2010 15:31:37 -0400 Received: from source ([65.219.4.130]) (using TLSv1) by na3sys009aob111.postini.com ([74.125.148.12]) with SMTP ID DSNKTK9xmJYiNQ/ytaXtsVyfVlLAa1TNxF7W@postini.com; Fri, 08 Oct 2010 12:31:37 PDT Received: from SC-vEXCH3.marvell.com ([10.93.76.133]) by sc-owa02.marvell.com ([10.93.76.22]) with mapi; Fri, 8 Oct 2010 12:31:35 -0700 From: Philip Rakity To: "linux-mmc@vger.kernel.org" Date: Fri, 8 Oct 2010 12:31:34 -0700 Subject: [PATCH] sdhci: 8 bit widths - allow new QUIRK for 8 bit and v3 sd controller Thread-Topic: [PATCH] sdhci: 8 bit widths - allow new QUIRK for 8 bit and v3 sd controller Thread-Index: ActnH2tE7vK+QMO2RD659eeXfkd9VA== Message-ID: <74C0C915-257F-41CC-AEA8-C6F5B839586B@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 08 Oct 2010 19:31:57 +0000 (UTC) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ea8472b..90cfdfb 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1189,6 +1189,18 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) host->ops->platform_send_init_74_clocks(host, ios->power_mode); ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + if (ios->bus_width == MMC_BUS_WIDTH_8) { + ctrl &= ~SDHCI_CTRL_4BITBUS; + if (host->version >= SDHCI_SPEC_300) + ctrl |= SDHCI_CTRL_8BITBUS; + } else { + if (host->version >= SDHCI_SPEC_300) + ctrl &= ~SDHCI_CTRL_8BITBUS; + if (ios->bus_width == MMC_BUS_WIDTH_4) + ctrl |= SDHCI_CTRL_4BITBUS; + else + ctrl &= ~SDHCI_CTRL_4BITBUS; + } if (ios->bus_width == MMC_BUS_WIDTH_8) ctrl |= SDHCI_CTRL_8BITBUS; @@ -1848,8 +1860,16 @@ int sdhci_add_host(struct sdhci_host *host) mmc->f_max = host->max_clk; mmc->caps |= MMC_CAP_SDIO_IRQ; - if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) - mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; + /* + * 8 bit width may be supported by v3 controller but not board. + * so the safest thing is to let the adaptation layer decide + * what to do by using the quirk + */ + if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) { + mmc->caps |= MMC_CAP_4_BIT_DATA; + if (host->quirks & SDHCI_QUIRK_SLOT_CAN_DO_8_BITS) + mmc->caps |= MMC_CAP_8_BIT_DATA; + } if (caps & SDHCI_CAN_DO_HISPD) mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 38ae340..c87e3c4 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -76,7 +76,7 @@ #define SDHCI_CTRL_ADMA1 0x08 #define SDHCI_CTRL_ADMA32 0x10 #define SDHCI_CTRL_ADMA64 0x18 -#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_8BITBUS 0x20 #define SDHCI_POWER_CONTROL 0x29 #define SDHCI_POWER_ON 0x01 @@ -152,6 +152,7 @@ #define SDHCI_CLOCK_BASE_SHIFT 8 #define SDHCI_MAX_BLOCK_MASK 0x00030000 #define SDHCI_MAX_BLOCK_SHIFT 16 +#define SDHCI_CAN_DO_8BIT 0x00040000 #define SDHCI_CAN_DO_ADMA2 0x00080000 #define SDHCI_CAN_DO_ADMA1 0x00100000 #define SDHCI_CAN_DO_HISPD 0x00200000 diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index 1fdc673..5be1cfc 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -83,6 +83,8 @@ struct sdhci_host { #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) +/* slot has 8 data pins going to eMMC/mmc card */ +#define SDHCI_QUIRK_SLOT_CAN_DO_8_BITS (1<<30) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */