From patchwork Thu Apr 23 08:17:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuninori Morimoto X-Patchwork-Id: 6260231 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 592189F389 for ; Thu, 23 Apr 2015 08:17:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5305320149 for ; Thu, 23 Apr 2015 08:17:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2267920383 for ; Thu, 23 Apr 2015 08:17:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755790AbbDWIRa (ORCPT ); Thu, 23 Apr 2015 04:17:30 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:35779 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751758AbbDWIR1 (ORCPT ); Thu, 23 Apr 2015 04:17:27 -0400 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie3.idc.renesas.com with ESMTP; 23 Apr 2015 17:17:26 +0900 Received: from relmlac4.idc.renesas.com (relmlac4.idc.renesas.com [10.200.69.24]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 5AB765B1C3; Thu, 23 Apr 2015 17:17:26 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 5670E480A5; Thu, 23 Apr 2015 17:17:26 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 4F750480A3; Thu, 23 Apr 2015 17:17:26 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac4.idc.renesas.com with ESMTP id TAC09097; Thu, 23 Apr 2015 17:17:26 +0900 X-IronPort-AV: E=Sophos;i="5.11,629,1422889200"; d="scan'208";a="185840108" Received: from mail-hk1lp0126.outbound.protection.outlook.com (HELO APAC01-HK1-obe.outbound.protection.outlook.com) ([207.46.51.126]) by relmlii2.idc.renesas.com with ESMTP/TLS/AES256-SHA; 23 Apr 2015 17:17:25 +0900 Authentication-Results: linaro.org; dkim=none (message not signed) header.d=none; Received: from morimoto-PC.renesas.com (211.11.155.132) by SIXPR06MB320.apcprd06.prod.outlook.com (10.141.125.150) with Microsoft SMTP Server (TLS) id 15.1.136.25; Thu, 23 Apr 2015 08:17:23 +0000 Message-ID: <874mo7gsza.wl%kuninori.morimoto.gx@renesas.com> From: Kuninori Morimoto Subject: [PATCH 5/7 v4] mmc: sh_mmcif: calculate best clock with parent clock User-Agent: Wanderlust/2.15.9 Emacs/24.3 Mule/6.0 To: Ulf Hansson , Simon CC: linux-mmc , Magnus , Linux-SH , Laurent , kobayashi In-Reply-To: <87d22vgt8u.wl%kuninori.morimoto.gx@renesas.com> References: <873840a4ch.wl%kuninori.morimoto.gx@renesas.com> <87d22vgt8u.wl%kuninori.morimoto.gx@renesas.com> MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Date: Thu, 23 Apr 2015 08:17:23 +0000 X-Originating-IP: [211.11.155.132] X-ClientProxiedBy: TY1PR0201CA0012.apcprd02.prod.outlook.com (25.164.90.150) To SIXPR06MB320.apcprd06.prod.outlook.com (10.141.125.150) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SIXPR06MB320; X-Forefront-Antispam-Report: BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(19580395003)(42186005)(53416004)(87976001)(62966003)(92566002)(86362001)(23726002)(77096005)(54356999)(5001770100001)(50986999)(77156002)(47776003)(76176999)(19580405001)(36756003)(229853001)(66066001)(33646002)(122386002)(40100003)(4001350100001)(46406003)(2950100001)(50466002)(83506001)(46102003)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:SIXPR06MB320; H:morimoto-PC.renesas.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002010)(5005006); SRVR:SIXPR06MB320; BCL:0; PCL:0; RULEID:; SRVR:SIXPR06MB320; X-Forefront-PRVS: 0555EC8317 X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2015 08:17:23.4682 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SIXPR06MB320 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kuninori Morimoto MMCIF IP on R-Car series has parent clock which can be set several rate, and it was not implemented on old SH-Mobile series (= SH-Mobile series parent clock was fixed rate) R-Car series MMCIF can use more high speed access if it setup parent clock. This patch adds parent clock setup method, and r8a7790/r8a7791 can use it. Signed-off-by: Kuninori Morimoto Tested-by: Keita Kobayashi --- v3 -> v4 - add new clk-range on DT - use clk_round_rate() for parent_clk - struct sh_mmcif_ver instead of sh_mmcif_parent_clk .../devicetree/bindings/mmc/renesas,mmcif.txt | 3 + drivers/mmc/host/sh_mmcif.c | 89 +++++++++++++++++++++- 2 files changed, 90 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt index 299081f..eb50f4e 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt +++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt @@ -14,6 +14,8 @@ Required properties: - clocks: reference to the functional clock +- clk-range: parent clock range + - dmas: reference to the DMA channels, one per channel name listed in the dma-names property. - dma-names: must contain "tx" for the transmit DMA channel and "rx" for the @@ -29,4 +31,5 @@ Example: R8A7790 (R-Car H2) MMCIF0 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; dma-names = "tx", "rx"; + clk-range = <12187500 97500000>; }; diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index d2f1158..437aa3c 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include @@ -224,6 +225,13 @@ enum mmcif_wait_for { MMCIF_WAIT_FOR_STOP, }; +/* + * difference for each SoC + */ +struct sh_mmcif_ver { + u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ +}; + struct sh_mmcif_host { struct mmc_host *mmc; struct mmc_request *mrq; @@ -248,6 +256,7 @@ struct sh_mmcif_host { bool ccs_enable; /* Command Completion Signal support */ bool clk_ctrl2_enable; struct mutex thread_lock; + const struct sh_mmcif_ver *ver; /* DMA support */ struct dma_chan *chan_rx; @@ -256,8 +265,14 @@ struct sh_mmcif_host { bool dma_active; }; +static const struct sh_mmcif_ver sh_mmcif_gen2 = { + .clkdiv_map = 0x3ff, +}; + static const struct of_device_id mmcif_of_match[] = { { .compatible = "renesas,sh-mmcif" }, + { .compatible = "renesas,mmcif-r8a7790", .data = &sh_mmcif_gen2}, + { .compatible = "renesas,mmcif-r8a7791", .data = &sh_mmcif_gen2}, { } }; MODULE_DEVICE_TABLE(of, mmcif_of_match); @@ -490,12 +505,50 @@ static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) if (!clk) return; - if (sup_pclk && clk == current_clk) + + if (host->ver) { + const struct sh_mmcif_ver *ver = host->ver; + unsigned int freq, best_freq, myclk, clkdiv, div, diff_min, diff; + int i; + + clkdiv = 0; + diff_min = ~0; + best_freq = 0; + for (i = fls(ver->clkdiv_map); i >= 0; i--) { + if (!((1 << i) & ver->clkdiv_map)) + continue; + + /* + * clk = parent_freq / div + * -> parent_freq = clk x div + */ + + div = 1 << (i + 1); + freq = clk_round_rate(host->clk, clk * div); + myclk = freq / div; + diff = (myclk > clk) ? myclk - clk : clk - myclk; + + if (diff <= diff_min) { + best_freq = freq; + clkdiv = i; + diff_min = diff; + } + } + + dev_dbg(&host->pd->dev, "clk %u/%u (%u, 0x%x)\n", + (best_freq / (1 << (clkdiv + 1))), clk, + best_freq, clkdiv); + + clk_set_rate(host->clk, best_freq); + sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, + CLK_CLEAR & (clkdiv << 16)); + } else if (sup_pclk && clk == current_clk) { sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); - else + } else { sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & ((fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16)); + } sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); } @@ -980,10 +1033,42 @@ static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) { + struct device *dev = &host->pd->dev; + const struct of_device_id *of_id = of_match_device(mmcif_of_match, dev); unsigned int clk = clk_get_rate(host->clk); + if (of_id) { + struct device_node *np = dev->of_node; + const struct sh_mmcif_ver *ver = of_id->data; + u32 range[2]; /* min/max */ + + if (!ver) + goto sh_mmcif_clk_setup_default; + + if (0 != of_property_read_u32_array(np, "clk-range", + range, ARRAY_SIZE(range))) + goto sh_mmcif_clk_setup_default; + + if (range[0] > range[1]) + goto sh_mmcif_clk_setup_default; + + host->mmc->f_min = range[0] / (1 << fls(ver->clkdiv_map)); + host->mmc->f_max = range[1] / (1 << ffs(ver->clkdiv_map)); + + dev_dbg(dev, "parent clk <%d - %d> (%d/%d)\n", + range[0], range[1], + host->mmc->f_max, host->mmc->f_min); + + host->ver = ver; + return; + } + +sh_mmcif_clk_setup_default: host->mmc->f_max = clk / 2; host->mmc->f_min = clk / 512; + + dev_dbg(dev, "clk max/min = %d/%d\n", + host->mmc->f_max, host->mmc->f_min); } static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)