From patchwork Fri Apr 22 20:25:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Rakity X-Patchwork-Id: 728041 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3MKPvBT005353 for ; Fri, 22 Apr 2011 20:25:57 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752647Ab1DVUZ5 (ORCPT ); Fri, 22 Apr 2011 16:25:57 -0400 Received: from na3sys009aog110.obsmtp.com ([74.125.149.203]:50368 "EHLO na3sys009aog110.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752128Ab1DVUZ5 convert rfc822-to-8bit (ORCPT ); Fri, 22 Apr 2011 16:25:57 -0400 Received: from SC-OWA01.marvell.com ([65.219.4.129]) (using TLSv1) by na3sys009aob110.postini.com ([74.125.148.12]) with SMTP ID DSNKTbHkUsWe5IsMBRH54EIjfs1H/CR8I/jT@postini.com; Fri, 22 Apr 2011 13:25:56 PDT Received: from SC-vEXCH3.marvell.com ([10.93.76.133]) by SC-OWA01.marvell.com ([10.93.76.21]) with mapi; Fri, 22 Apr 2011 13:23:13 -0700 From: Philip Rakity To: "linux-mmc@vger.kernel.org" CC: Arindam Nath Date: Fri, 22 Apr 2011 13:25:45 -0700 Subject: [PATCH] sdhci-pxa: add platform specific code for UHS signaling Thread-Topic: [PATCH] sdhci-pxa: add platform specific code for UHS signaling Thread-Index: AcwBK3bZD7r7ghg7QVqTyQpwT+zNWg== Message-ID: <95F7D594-60D3-49AA-87DA-63B5970D9787@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 22 Apr 2011 20:25:58 +0000 (UTC) Marvell controller requires 1.8V bit in UHS control register 2 be set when doing UHS. eMMC does not require 1.8V for DDR. add platform code to handle this. Signed-off-by: Philip Rakity --- drivers/mmc/host/sdhci-pxa.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 38 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/host/sdhci-pxa.c b/drivers/mmc/host/sdhci-pxa.c index 0e64d66..279d677 100644 --- a/drivers/mmc/host/sdhci-pxa.c +++ b/drivers/mmc/host/sdhci-pxa.c @@ -94,7 +94,42 @@ static void platform_reset_exit(struct sdhci_host *host, u8 mask) } } +static int set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) +{ + u16 ctrl_2; + + /* + * Set V18_EN -- UHS modes do not work without this. + * does not change signaling voltage + */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + if (uhs == MMC_TIMING_UHS_SDR12) + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + else if (uhs == MMC_TIMING_UHS_SDR25) + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + else if (uhs == MMC_TIMING_UHS_SDR50) { + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + ctrl_2 |= SDHCI_CTRL_VDD_180; + } + else if (uhs == MMC_TIMING_UHS_SDR104) { + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + ctrl_2 |= SDHCI_CTRL_VDD_180; + } + else if (uhs == MMC_TIMING_UHS_DDR50) { + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + ctrl_2 |= SDHCI_CTRL_VDD_180; + } + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + pr_debug("%s:%s uhs = %d, ctrl_2 = %04X\n", + __func__, mmc_hostname(host->mmc), uhs, ctrl_2); + return 0; +} + static struct sdhci_ops sdhci_pxa_ops = { + .set_uhs_signaling = set_uhs_signaling, .platform_reset_exit = platform_reset_exit, }; @@ -172,6 +207,9 @@ static int __devinit sdhci_pxa_probe(struct platform_device *pdev) /* enable mmc bus width testing */ host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; + /* enable 1/8V DDR capable */ + host->mmc->caps |= MMC_CAP_1_8V_DDR; + /* If slot design supports 8 bit data, indicate this to MMC. */ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) host->mmc->caps |= MMC_CAP_8_BIT_DATA;