From 6b82bd3c0fe55b7060b8d96801e5e2c4fecc79b7 Mon Sep 17 00:00:00 2001
From: Zhangfei Gao <zgao6@marvell.com>
Date: Fri, 20 Aug 2010 14:02:36 -0400
Subject: [PATCH] sdhci: base clock freqency change in spec 3.0
sdhc spec 3.0: Capabilities Register bits[15-08] is Base Clock Freqency
sdhc spec 1.0 & 2.0: Capabilities Register bits[13-08] is Base Clock Freqency
Signed-off-by: Zhangfei Gao <zgao6@marvell.com>
---
drivers/mmc/host/sdhci.c | 8 ++++++--
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
@@ -1778,8 +1778,12 @@ int sdhci_add_host(struct sdhci_host *host)
mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
}
- host->max_clk =
- (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+ if (host->version >= SDHCI_SPEC_300)
+ host->max_clk =
+ (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+ else
+ host->max_clk =
+ (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
host->max_clk *= 1000000;
if (host->max_clk == 0 || host->quirks &
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
@@ -140,6 +140,7 @@
#define SDHCI_TIMEOUT_CLK_SHIFT 0
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
#define SDHCI_CLOCK_BASE_MASK 0x00003F00
+#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
#define SDHCI_CLOCK_BASE_SHIFT 8
#define SDHCI_MAX_BLOCK_MASK 0x00030000
#define SDHCI_MAX_BLOCK_SHIFT 16
--
1.7.0.4