| Message ID | CWXP265MB26803AE79E0AD5ED083BF2A6C4529@CWXP265MB2680.GBRP265.PROD.OUTLOOK.COM (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] mmc: enable UHS voltage switch for SDSC if supported | expand |
On Wed, 12 May 2021 at 18:03, Christian Löhle <CLoehle@hyperstone.com> wrote: > > Ignore the reported capacity if the card otherwise reports UHS support. > > Let SDSC cards reporting UHS support (except for the CCS) attempt the > voltage switch. > Up until now such cards would be initialized as UHS, > supporting UHS features SDSC cards are otherwise barred from, > but skip the voltage switch. > While strictly speaking a SDSC card cannot support UHS in compliance > with the standard, there is no good reason to throttle them that way. > Especially for pSLCs in practice such cards benefit greatly, > as they can be new and UHS supporting, but must not lie about their CCS. > > Signed-off-by: Christian Loehle <cloehle@hyperstone.com> Apologize for the delay. I have tested a bunch of my old (and new) SD/uSD cards, this seems to work fine. I have applied this for next, but I think this actually should be considered as bug fix. I let it cook in linux-next for a while, then I will probably add a stable tag for it. Thanks and kind regards Uffe > --- > drivers/mmc/core/sd.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c > index 2c48d6504101..62d02f1dc924 100644 > --- a/drivers/mmc/core/sd.c > +++ b/drivers/mmc/core/sd.c > @@ -847,11 +847,17 @@ int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid, u32 *rocr) > return err; > > /* > - * In case CCS and S18A in the response is set, start Signal Voltage > + * In case S18A in the response is set, start Signal Voltage > * Switch procedure. SPI mode doesn't support CMD11. > + * Strictly speaking, S18A is not valid if CCS is not set (= not SDSC), > + * so one would have to OCR for 0x41000000. > + * We choose to ignore this as SDSC cards that report UHS voltage > + * support should not be throttled artificially by the standard this > + * way. > + * SDSC cards that 'accidentally' reporting UHS support by setting the > + * reserved bits don't seem to be an issue in practice. > */ > - if (!mmc_host_is_spi(host) && rocr && > - ((*rocr & 0x41000000) == 0x41000000)) { > + if (!mmc_host_is_spi(host) && rocr && (*rocr & 0x01000000)) { > err = mmc_set_uhs_voltage(host, pocr); > if (err == -EAGAIN) { > retries--; > @@ -1109,7 +1115,14 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, > } > } > > - /* Initialization sequence for UHS-I cards */ > + /* Initialization sequence for UHS-I cards > + * Strictly speaking, S18A in the OCR is only valid if CCS is set, too. > + * So SDSC cards should be excluded. We choose to deviate from the > + * standard here to allow SDSC cards to utilize UHS if they report > + * supporting it. > + * Fortunately, SDSC cards reporting S18A and the related bus speed > + * modes on accident, by setting reserved bits, don't seem to exist. > + */ > if (rocr & SD_ROCR_S18A && mmc_host_uhs(host)) { > err = mmc_sd_init_uhs_card(card); > if (err) > -- > 2.31.1 > > Hyperstone GmbH | Line-Eid-Strasse 3 | 78467 Konstanz > Managing Directors: Dr. Jan Peter Berns. > Commercial register of local courts: Freiburg HRB381782 >
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 2c48d6504101..62d02f1dc924 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -847,11 +847,17 @@ int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid, u32 *rocr) return err; /* - * In case CCS and S18A in the response is set, start Signal Voltage + * In case S18A in the response is set, start Signal Voltage * Switch procedure. SPI mode doesn't support CMD11. + * Strictly speaking, S18A is not valid if CCS is not set (= not SDSC), + * so one would have to OCR for 0x41000000. + * We choose to ignore this as SDSC cards that report UHS voltage + * support should not be throttled artificially by the standard this + * way. + * SDSC cards that 'accidentally' reporting UHS support by setting the + * reserved bits don't seem to be an issue in practice. */ - if (!mmc_host_is_spi(host) && rocr && - ((*rocr & 0x41000000) == 0x41000000)) { + if (!mmc_host_is_spi(host) && rocr && (*rocr & 0x01000000)) { err = mmc_set_uhs_voltage(host, pocr); if (err == -EAGAIN) { retries--; @@ -1109,7 +1115,14 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, } } - /* Initialization sequence for UHS-I cards */ + /* Initialization sequence for UHS-I cards + * Strictly speaking, S18A in the OCR is only valid if CCS is set, too. + * So SDSC cards should be excluded. We choose to deviate from the + * standard here to allow SDSC cards to utilize UHS if they report + * supporting it. + * Fortunately, SDSC cards reporting S18A and the related bus speed + * modes on accident, by setting reserved bits, don't seem to exist. + */ if (rocr & SD_ROCR_S18A && mmc_host_uhs(host)) { err = mmc_sd_init_uhs_card(card); if (err)
Ignore the reported capacity if the card otherwise reports UHS support. Let SDSC cards reporting UHS support (except for the CCS) attempt the voltage switch. Up until now such cards would be initialized as UHS, supporting UHS features SDSC cards are otherwise barred from, but skip the voltage switch. While strictly speaking a SDSC card cannot support UHS in compliance with the standard, there is no good reason to throttle them that way. Especially for pSLCs in practice such cards benefit greatly, as they can be new and UHS supporting, but must not lie about their CCS. Signed-off-by: Christian Loehle <cloehle@hyperstone.com> --- drivers/mmc/core/sd.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-)