From patchwork Wed May 15 05:50:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 2569961 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 64DA0DF2A2 for ; Wed, 15 May 2013 05:51:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751795Ab3EOFvJ (ORCPT ); Wed, 15 May 2013 01:51:09 -0400 Received: from moutng.kundenserver.de ([212.227.17.9]:62350 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751300Ab3EOFvI (ORCPT ); Wed, 15 May 2013 01:51:08 -0400 Received: from axis700.grange (dslb-088-077-162-247.pools.arcor-ip.net [88.77.162.247]) by mrelayeu.kundenserver.de (node=mrbap4) with ESMTP (Nemesis) id 0MY6Rk-1UyXj12zR2-00UunF; Wed, 15 May 2013 07:50:51 +0200 Received: by axis700.grange (Postfix, from userid 1000) id 2D32E40BB4; Wed, 15 May 2013 07:50:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by axis700.grange (Postfix) with ESMTP id 2A24C40BB3; Wed, 15 May 2013 07:50:51 +0200 (CEST) Date: Wed, 15 May 2013 07:50:51 +0200 (CEST) From: Guennadi Liakhovetski X-X-Sender: lyakh@axis700.grange To: linux-mmc@vger.kernel.org cc: linux-sh@vger.kernel.org, Nguyen Viet Dung , Magnus Damm , Chris Ball Subject: [PATCH] mmc: mmcif: don't clear masked interrupts Message-ID: MIME-Version: 1.0 X-Provags-ID: V02:K0:lCXzYiuTv0LJF194YbsAy1Q5kkT8SIrLW11rzPyuoaX DImI72K5JW9o0s+if6M/hYgYWLpLEv0pQwOpBvnwf6ZLwv8/um /E5nYl+/+7vdrt0bp/y6XkAtN4aGrdNYELss6wzpWmqG4igRvU wtfXoXJy5DpC0wfKSjqRpZ1TfYdewtpY+Agvd5nUDITN0Ck52d EnNfghhAbFZXjoDRQWE68ywuTI+8ftHsvsC2MhZEjnN9GDcfD4 TNtaskWWkPgKJXJuOiqf5DpQ3ykOEibDAXo33QCbYQEuh3m1Q4 gN0juj7AV1mCOr/P37KEwO+TElFf58cFvNDXbNstVbE3kityPn Pt1OhLZQL/GyHTm/TSfcjpAY+povW4kWcav6Pd27SeeqC+1OMP 7TncUOW3NUX3Q== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Masking events on MMCIF means, an occurrence of the masked event won't raise an interrupt, but the event bit will still be set in the interrupt status register. If simultaneously a different event occurs, that was enabled, both flags will be set. However, only the unmasked event bit should be cleared in the status register in such a case. Clearing also the masked bit can lead to lost interrupts, which indeed can be observed on the armadillo800eva r8a7740 board with an eMMC chip. The problem has been introduced by the recent "mmc: sh_mmcif: simplify IRQ processing" patch. Fix the problem by only clearing enabled interrupts. Signed-off-by: Guennadi Liakhovetski Reported-by: Nguyen Viet Dung tested-by: Nguyen Viet Dung Tested-by: Kuninori Morimoto --- Chris, please, push this fix to 3.10, thanks. drivers/mmc/host/sh_mmcif.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index ba76a53..06caaae 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -1244,7 +1244,8 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) u32 state; state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); - sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); + sh_mmcif_writel(host->addr, MMCIF_CE_INT, + ~(state & sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK))); sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); if (state & ~MASK_CLEAN)