From patchwork Tue Apr 4 19:03:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiner Kallweit X-Patchwork-Id: 9662443 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 653B96032D for ; Tue, 4 Apr 2017 19:11:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5687928546 for ; Tue, 4 Apr 2017 19:11:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 49ED928551; Tue, 4 Apr 2017 19:11:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E60C628546 for ; Tue, 4 Apr 2017 19:11:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754931AbdDDTL2 (ORCPT ); Tue, 4 Apr 2017 15:11:28 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:36162 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753852AbdDDTL1 (ORCPT ); Tue, 4 Apr 2017 15:11:27 -0400 Received: by mail-wm0-f65.google.com with SMTP id x124so7505710wmf.3 for ; Tue, 04 Apr 2017 12:11:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:references:cc:from:message-id:date:user-agent :mime-version:in-reply-to:content-transfer-encoding; bh=R2etZBhbE8O2mwTicJM9WfCrmzOsIF87P4DD3GV/cG0=; b=VJX5Yq+JGqPPdCM9gbMzo/8Eb8WuHqgCUH7l/6e1RpdLNETF+yErPZuiJe3YX2n9hu FeCiFLsvWzm692LN760hr8vwVrlWVmAvjlaZSMpvptfCXub67cjmn3z58yCWV1lzRN+w mHvxJsvsb6tXqoCA6YtTCQK602WiRGZw/99klxurzUGPFJ3js6XPO9hDDt3BUaXbuRda 9RoyzopUnR0tHQoqunuy8pei8hvWPA9YRZEzTWpnAVljzNj7vDtdBHSNRJusbPbVFEcf 2oKOa4VNf+ZsvFVCJi3SQ/hZ5RAeyNoqu3SiWoxnsmho3OODB/nlnR0cB0Gi1PFX7gYh nwrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:cc:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding; bh=R2etZBhbE8O2mwTicJM9WfCrmzOsIF87P4DD3GV/cG0=; b=DoiS0WwfoSARLXUQDM82EH0tbcEDfnp7+Im7lVTp2IM58MEZAgrSFHfrpsd6oH62oA 01DUjoZKAmZ4Nl+3WI7R1xIbJbE6IvdvFv8jGLhpRXU15QN03kQMDGq/fB4+e8MgPDh2 I9XnhB9pe+Zh3/C5COmA+TPNo0lc9Hc8OS+ic0jeir1d/rv2EaqyaZQPxZM7ZBobGs5/ F9gH2FnYcY/Wh8AV+qJhVCpQJK7orKhKyymYF1wl775KYQTLuZBLh6u5Eh1UnnebIebf t5gl1KioboMOS9QiXR5VvQjiJ8Ux9u6hbXHnd4Sn1rWfazonPFcDW2CrDq97kTZ3eLyN xsiQ== X-Gm-Message-State: AFeK/H20LKdOxj7IWFkxQxcJ5SOVlkjwOOmS0eVqWOd5vZyVIIK4gtFl1db4RXv3dIo1ag== X-Received: by 10.28.181.78 with SMTP id e75mr9644077wmf.105.1491333085702; Tue, 04 Apr 2017 12:11:25 -0700 (PDT) Received: from ?IPv6:2003:c6:ebdc:4000:c0d5:60a1:c236:c60b? (p200300C6EBDC4000C0D560A1C236C60B.dip0.t-ipconnect.de. [2003:c6:ebdc:4000:c0d5:60a1:c236:c60b]) by smtp.googlemail.com with ESMTPSA id w93sm23442954wrb.3.2017.04.04.12.11.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Apr 2017 12:11:24 -0700 (PDT) Subject: [PATCH 1/2] mmc: meson-gx: introduce struct meson_tuning_params To: Ulf Hansson , Kevin Hilman References: <1d60ec2c-54c9-6b1c-7eaa-40e96fcd5be5@gmail.com> Cc: "linux-mmc@vger.kernel.org" , linux-amlogic@lists.infradead.org From: Heiner Kallweit Message-ID: Date: Tue, 4 Apr 2017 21:03:22 +0200 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <1d60ec2c-54c9-6b1c-7eaa-40e96fcd5be5@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce struct meson_tuning_params for storing the clock phase configurations. There's no functional change because tx and rx clock phase were implicitely set to CLK_PHASE_0 before. Signed-off-by: Heiner Kallweit --- drivers/mmc/host/meson-gx-mmc.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 0036680b..3a6e51c8 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -49,6 +49,8 @@ #define CLK_SRC_PLL 1 /* FCLK_DIV2 */ #define CLK_SRC_PLL_RATE 1000000000 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) +#define CLK_TX_PHASE_MASK GENMASK(11, 10) +#define CLK_RX_PHASE_MASK GENMASK(13, 12) #define CLK_PHASE_0 0 #define CLK_PHASE_90 1 #define CLK_PHASE_180 2 @@ -111,6 +113,12 @@ #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ #define MUX_CLK_NUM_PARENTS 2 +struct meson_tuning_params { + u8 core_phase; + u8 tx_phase; + u8 rx_phase; +}; + struct meson_host { struct device *dev; struct mmc_host *mmc; @@ -130,6 +138,7 @@ struct meson_host { void *bounce_buf; dma_addr_t bounce_dma_addr; + struct meson_tuning_params tp; bool vqmmc_enabled; }; @@ -312,7 +321,9 @@ static int meson_mmc_clk_init(struct meson_host *host) /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ clk_reg = 0; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL); clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX); clk_reg &= ~CLK_ALWAYS_ON; @@ -757,6 +768,10 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto free_host; + host->tp.core_phase = CLK_PHASE_180; + host->tp.tx_phase = CLK_PHASE_0; + host->tp.rx_phase = CLK_PHASE_0; + ret = meson_mmc_clk_init(host); if (ret) goto err_core_clk;