From patchwork Fri Oct 7 15:22:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 9366321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 51233608A6 for ; Fri, 7 Oct 2016 15:26:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 418F3296C3 for ; Fri, 7 Oct 2016 15:26:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 34543296E5; Fri, 7 Oct 2016 15:26:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 781A4296C3 for ; Fri, 7 Oct 2016 15:26:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933508AbcJGP0X (ORCPT ); Fri, 7 Oct 2016 11:26:23 -0400 Received: from down.free-electrons.com ([37.187.137.238]:34931 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1757116AbcJGPZD (ORCPT ); Fri, 7 Oct 2016 11:25:03 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 5E4832074; Fri, 7 Oct 2016 17:24:37 +0200 (CEST) Received: from localhost (83.146.29.93.rev.sfr.net [93.29.146.83]) by mail.free-electrons.com (Postfix) with ESMTPSA id E519D372; Fri, 7 Oct 2016 17:24:18 +0200 (CEST) From: Gregory CLEMENT To: Ulf Hansson , Adrian Hunter , linux-mmc@vger.kernel.org Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT , Rob Herring , devicetree@vger.kernel.org, Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Ziji Hu , "Jack(SH) Zhu" , Jimmy Xu , Jisheng Zhang , Nadav Haklai , Ryan Gao , Doug Jones , Shiwu Zhang , Victor Gu , "Wei(SOCP) Liu" , Wilson Ding , Xueping Liu , Hilbert Zhang , Keji Zhang , Liuliu Zhao , Peng Zhu , Yu Cao , Romain Perier , Yehuda Yitschak , Marcin Wojtas , Hanna Hawa , Kostya Porotchkin , linux-kernel@vger.kernel.org Subject: [PATCH 5/10] dt: bindings: Add bindings for Marvell Xenon SD Host Controller Date: Fri, 7 Oct 2016 17:22:51 +0200 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ziji Hu Marvell Xenon SDHC can support eMMC/SD/SDIO. Add Xenon-specific properties. Also add properties for Xenon PHY setting. Signed-off-by: Hu Ziji Reviewed-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt | 164 +++++++- MAINTAINERS | 1 +- 2 files changed, 165 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt diff --git a/Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt b/Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt new file mode 100644 index 000000000000..8b25ad28ebbd --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt @@ -0,0 +1,164 @@ +Marvell's Xenon SDHCI Controller device tree bindings +This file documents differences between the core mmc properties +described by mmc.txt and the properties used by the Xenon implementation. + +A single Xenon IP can support multiple slots. +Each slot acts as an independent SDHC. It owns independent resources, such +as register sets clock and PHY. +Each slot should have an independent device tree node. + +Required Properties: +- compatible: should be "marvell,sdhci-xenon" or "marvell,armada-3700-sdhci". + +- Input Clock Name + Some SOCs require additional clock for AXI bus. + The input clock for Xenon IP core should be named as "core". + The optional AXI clock should be named as "axi". + - clocks = <&core_clk>, <&axi_clock>; + - clock-names = "core", "axi"; + +- Register Set Size + Different Xenon SDHC release has different register set size. + The specific size should also refer to the SOC implementation. + +Optional Properties: +- Slot Index + A single Xenon IP can support multiple slots. + During initialization, each slot should set corresponding setting bit in + some Xenon-specific registers. The corresponding bit is determined by + this property. + - xenon,slotno = ; + If this property is not provided, Xenon IP should contain only one slot + and the slot index will be 0x0 by default. + +- PHY Type + Xenon support mutilple types of PHYs. + To select eMMC 5.1 PHY, set: + - xenon,phy-type = "emmc 5.1 phy" + eMMC 5.1 PHY is the default choice if this property is not provided. + To select eMMC 5.0 PHY, set: + - xenon,phy-type = "emmc 5.0 phy" + To select SDH PHY, set: + - xenon,phy-type = "sdh phy" + Please note that eMMC PHY is a general PHY for eMMC/SD/SDIO, other than for + eMMC only. + +- Customized eMMC PHY Parameters + Some boards require different values of some specific eMMC PHY parameters. + Some SOCs also require specific workaround to set eMMC PHY. + These properties enable diverse boards to customize the eMMC PHY. + The supported eMMC PHY parameters are listed in below. All those properties + are only available for eMMC PHY 5.1 and eMMC PHY 5.0. + ZNR + valid range = [0:0x1F]. + ZNR is set as 0xF by default if this property is not provided. + - xenon,phy-znr = ; + + ZPR + valid range = [0:0x1F]. + ZPR is set as 0xF by default if this property is not provided. + - xenon,phy-zpr = ; + + Number of successful tuning times + Set the number of required consecutive successful sampling points used to + identify a valid sampling window, in tuning process. + Valid range = [1:7]. Set as 0x4 by default if this property is not provided. + - xenon,phy-nr-tun-times = ; + + Divider for TUN_STEP + Set the divider for calculating TUN_STEP. + Set as 64 by default if this property is not provided. + - xenon,phy-tun-step-divider = ; + + Force PHY into slow mode. + Only available when bus frequency lower than 50MHz in SDR mde. + Disabled by default. Please do not enable it unless it is necessary. + - xenon,phy-slow-mode; + +- Mask Conflict Error Report + Disable Conflict Error alert on some SOC. Disabled by default. + xenon,mask-conflict-err; + +- Re-tuning Counter + Xenon SDHC SOC usually doesn't provide re-tuning counter in + Capabilities Register 3 Bit[11:8]. + This property provides the re-tuning counter. + xenon,tuning-count = ; + If this property is not set, default re-tuning counter will + be set as 0x9 in driver. + +- SOC PHY PAD Voltage Control register + Some SOCs have SOC PHY PAD Voltage Control register outside Xenon IP. + This register sets SOC PHY PAD Voltage to keep aligh with Vccq. + Two properties provide information of this control register. + These two properties are only valid when "marvell,armada-3700-sdhci" + is selected. Both of them must be provided when "marvell,armada-3700-sdhci" + is selected. + - xenon,pad-type + Two types: "sd" and "fixed-1-8v". + If "sd" is slected, SOC PHY PAD is set as 3.3V at the beginning and is + switched to 1.8V when SD in UHS-I. + If "fixed-1-8v" is slected, SOC PHY PAD is fixed 1.8V, such as for eMMC. + - reg + Physical address and size of SOC PHY PAD register. + Append after Xenon SDHC register space, as a second register field. + + Please follow the examples with compatible "marvell,armada-3700-sdhci" + in below. + +Example: +- For eMMC slot: + + sdhci@aa0000 { + compatible = "marvell,sdhci-xenon"; + reg = <0xaa0000 0x1000>; + interrupts = + clocks = <&emmcclk>; + clock-names = "core"; + xenon,slotno = <0>; + xenon,phy-type = "emmc 5.1 phy"; + bus-width = <8>; + tuning-count = <11>; + }; + +- For SD/SDIO slot: + + sdhci@ab0000 { + compatible = "marvell,sdhci-xenon"; + reg = <0xab0000 0x1000>; + interrupts = + vqmmc-supply = <&sd_regulator>; + clocks = <&sdclk>; + clock-names = "core"; + bus-width = <4>; + tuning-count = <9>; + }; + +- For eMMC slot with compatible "marvell,armada-3700-sdhci": + + sdhci@aa0000 { + compatible = "marvell,armada-3700-sdhci"; + reg = <0xaa0000 0x1000>, + ; + interrupts = + clocks = <&emmcclk>; + clock-names = "core"; + bus-width = <8>; + + xenon,pad-type = "fixed-1-8v"; + }; + +- For SD/SDIO slot with compatible "marvell,armada-3700-sdhci": + + sdhci@ab0000 { + compatible = "marvell,armada-3700-sdhci"; + reg = <0xab0000 0x1000>, + ; + interrupts = + vqmmc-supply = <&sd_regulator>; + clocks = <&sdclk>; + clock-names = "core"; + bus-width = <4>; + + xenon,pad-type = "sd"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 89adcd57aa25..4aa0eac9bfc7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7582,6 +7582,7 @@ MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER M: Ziji Hu L: linux-mmc@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt MATROX FRAMEBUFFER DRIVER L: linux-fbdev@vger.kernel.org