| Message ID | fff139f001835efb5ee428093a9522d7761642de.1627204633.git.mirq-linux@rere.qmqm.pl (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | SDHCI clock handling fixes and cleanups | expand |
On 25/07/21 12:20 pm, Michał Mirosław wrote: > Fixed commit added an unnecessary read of CLOCK_CONTROL. The value read > is overwritten for programmable clock preset, but is carried over for > divided clock preset. This can confuse sdhci_enable_clk() if the register > has enable bits set for some reason at time time of clock calculation. "time time" -> "time" > Remove the read. > > Quoting Al Cooper: > > sdhci_brcmstb_set_clock() assumed that sdhci_calc_clk() would always > return the divider value without the enable set, so this fixes a case > for DDR52 where the enable was not being cleared when the divider > value was changed. > > Cc: stable@vger.kernel.org > Fixes: 52983382c74f ("mmc: sdhci: enhance preset value function") > Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> > Acked-by: Al Cooper <alcooperx@gmail.com> Apart from above: Acked-by: Adrian Hunter <adrian.hunter@intel.com> > > --- > v4: no changes > v3: updated commit message > v2: removed truncated sentence from commitmsg > > Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> > --- > drivers/mmc/host/sdhci.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > index aba6e10b8605..c7438dd13e3e 100644 > --- a/drivers/mmc/host/sdhci.c > +++ b/drivers/mmc/host/sdhci.c > @@ -1857,7 +1857,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, > if (host->preset_enabled) { > u16 pre_val; > > - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > pre_val = sdhci_get_preset_value(host); > div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); > if (host->clk_mul && >
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index aba6e10b8605..c7438dd13e3e 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1857,7 +1857,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, if (host->preset_enabled) { u16 pre_val; - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); pre_val = sdhci_get_preset_value(host); div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); if (host->clk_mul &&
Fixed commit added an unnecessary read of CLOCK_CONTROL. The value read is overwritten for programmable clock preset, but is carried over for divided clock preset. This can confuse sdhci_enable_clk() if the register has enable bits set for some reason at time time of clock calculation. Remove the read. Quoting Al Cooper: sdhci_brcmstb_set_clock() assumed that sdhci_calc_clk() would always return the divider value without the enable set, so this fixes a case for DDR52 where the enable was not being cleared when the divider value was changed. Cc: stable@vger.kernel.org Fixes: 52983382c74f ("mmc: sdhci: enhance preset value function") Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Al Cooper <alcooperx@gmail.com> --- v4: no changes v3: updated commit message v2: removed truncated sentence from commitmsg Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> --- drivers/mmc/host/sdhci.c | 1 - 1 file changed, 1 deletion(-)