@@ -197,24 +197,29 @@ void pat_init_cache_modes(void)
void pat_init(void)
{
u64 pat;
- bool boot_cpu = !boot_pat_state;
+ static bool boot_cpu_done;
if (!pat_enabled())
return;
- if (!cpu_has_pat) {
- if (!boot_pat_state) {
+ if (!boot_cpu_done) {
+ if (!cpu_has_pat) {
pat_disable("PAT not supported by CPU.");
return;
- } else {
- /*
- * If this happens we are on a secondary CPU, but
- * switched to PAT on the boot CPU. We have no way to
- * undo PAT.
- */
- pr_err("x86/PAT: PAT enabled, but not supported by secondary CPU\n");
- BUG();
}
+
+ rdmsrl(MSR_IA32_CR_PAT, boot_pat_state);
+ if (!boot_pat_state) {
+ pat_disable("PAT read returns always zero, disabled.");
+ return;
+ }
+ } else if (!cpu_has_pat) {
+ /*
+ * If this happens we are on a secondary CPU, but
+ * switched to PAT on the boot CPU. We have no way to
+ * undo PAT.
+ */
+ panic("PAT enabled, but not supported by secondary CPU\n");
}
/* Set PWT to Write-Combining. All other bits stay the same */
@@ -233,19 +238,12 @@ void pat_init(void)
pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
- /* Boot CPU check */
- if (!boot_pat_state) {
- rdmsrl(MSR_IA32_CR_PAT, boot_pat_state);
- if (!boot_pat_state) {
- pat_disable("PAT read returns always zero, disabled.");
- return;
- }
- }
-
wrmsrl(MSR_IA32_CR_PAT, pat);
- if (boot_cpu)
+ if (!boot_cpu_done) {
pat_init_cache_modes();
+ boot_cpu_done = true;
+ }
}
#undef PAT