From patchwork Fri Aug 25 20:59:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 9922839 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D95A660349 for ; Fri, 25 Aug 2017 21:00:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C9085284AA for ; Fri, 25 Aug 2017 21:00:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BC7C9284E3; Fri, 25 Aug 2017 21:00:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from ml01.01.org (ml01.01.org [198.145.21.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 600582847A for ; Fri, 25 Aug 2017 21:00:05 +0000 (UTC) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CDAF92095B9FD; Fri, 25 Aug 2017 13:57:28 -0700 (PDT) X-Original-To: linux-nvdimm@lists.01.org Delivered-To: linux-nvdimm@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6C1F42095B9C1 for ; Fri, 25 Aug 2017 13:57:27 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Aug 2017 13:59:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.41,426,1498546800"; d="scan'208"; a="1007722421" Received: from djiang5-desk3.ch.intel.com ([143.182.137.38]) by orsmga003.jf.intel.com with ESMTP; 25 Aug 2017 13:59:46 -0700 Subject: [PATCH v6 4/8] dmaengine: ioatdma: dma_prep_memcpy_sg support From: Dave Jiang To: vinod.koul@intel.com, dan.j.williams@intel.com Date: Fri, 25 Aug 2017 13:59:46 -0700 Message-ID: <150369478668.6962.13507203779322642480.stgit@djiang5-desk3.ch.intel.com> In-Reply-To: <150369446130.6962.4195769527575520889.stgit@djiang5-desk3.ch.intel.com> References: <150369446130.6962.4195769527575520889.stgit@djiang5-desk3.ch.intel.com> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-BeenThere: linux-nvdimm@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: "Linux-nvdimm developer list." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dmaengine@vger.kernel.org, hch@infradead.org, linux-nvdimm@lists.01.org Errors-To: linux-nvdimm-bounces@lists.01.org Sender: "Linux-nvdimm" X-Virus-Scanned: ClamAV using ClamSMTP Adding ioatdma support to copy from a physically contiguous buffer to a provided scatterlist and vice versa. This is used to support reading/writing persistent memory in the pmem driver. Signed-off-by: Dave Jiang --- drivers/dma/ioat/dma.h | 4 +++ drivers/dma/ioat/init.c | 2 ++ drivers/dma/ioat/prep.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 56200ee..6c08b06 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -370,6 +370,10 @@ struct dma_async_tx_descriptor * ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, dma_addr_t dma_src, size_t len, unsigned long flags); struct dma_async_tx_descriptor * +ioat_dma_prep_memcpy_sg_lock(struct dma_chan *c, + struct scatterlist *sg, unsigned int sg_nents, + dma_addr_t dma_addr, bool to_sg, unsigned long flags); +struct dma_async_tx_descriptor * ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags); struct dma_async_tx_descriptor * ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, diff --git a/drivers/dma/ioat/init.c b/drivers/dma/ioat/init.c index 1b881fb..5c69ff6 100644 --- a/drivers/dma/ioat/init.c +++ b/drivers/dma/ioat/init.c @@ -1081,6 +1081,8 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) dma = &ioat_dma->dma_dev; dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; + dma_cap_set(DMA_MEMCPY_SG, dma->cap_mask); + dma->device_prep_dma_memcpy_sg = ioat_dma_prep_memcpy_sg_lock; dma->device_issue_pending = ioat_issue_pending; dma->device_alloc_chan_resources = ioat_alloc_chan_resources; dma->device_free_chan_resources = ioat_free_chan_resources; diff --git a/drivers/dma/ioat/prep.c b/drivers/dma/ioat/prep.c index 243421a..d8219af 100644 --- a/drivers/dma/ioat/prep.c +++ b/drivers/dma/ioat/prep.c @@ -159,6 +159,63 @@ ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, return &desc->txd; } +struct dma_async_tx_descriptor * +ioat_dma_prep_memcpy_sg_lock(struct dma_chan *c, + struct scatterlist *sg, unsigned int sg_nents, + dma_addr_t dma_addr, bool to_sg, unsigned long flags) +{ + struct ioatdma_chan *ioat_chan = to_ioat_chan(c); + struct ioat_dma_descriptor *hw = NULL; + struct ioat_ring_ent *desc = NULL; + dma_addr_t dma_off = dma_addr; + int num_descs, idx, i; + struct scatterlist *s; + size_t total_len = 0, len; + + + if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + return NULL; + + /* + * The upper layer will garantee that each entry does not exceed + * xfercap. + */ + num_descs = sg_nents; + + if (likely(num_descs) && + ioat_check_space_lock(ioat_chan, num_descs) == 0) + idx = ioat_chan->head; + else + return NULL; + + for_each_sg(sg, s, sg_nents, i) { + desc = ioat_get_ring_ent(ioat_chan, idx + i); + hw = desc->hw; + len = sg_dma_len(s); + hw->size = len; + hw->ctl = 0; + if (to_sg) { + hw->src_addr = dma_off; + hw->dst_addr = sg_dma_address(s); + } else { + hw->src_addr = sg_dma_address(s); + hw->dst_addr = dma_off; + } + dma_off += len; + total_len += len; + dump_desc_dbg(ioat_chan, desc); + } + + desc->txd.flags = flags; + desc->len = total_len; + hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); + hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); + hw->ctl_f.compl_write = 1; + dump_desc_dbg(ioat_chan, desc); + /* we leave the channel locked to ensure in order submission */ + + return &desc->txd; +} static struct dma_async_tx_descriptor * __ioat_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result,