[v3,14/40] cxl/core: Track port depth

Message ID	164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com (mailing list archive)
State	Accepted
Commit	53fa1bff3426344d466d91e81f076eab677d0ece
Headers	show Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BE432CAE for <nvdimm@lists.linux.dev>; Mon, 24 Jan 2022 00:29:54 +0000 (UTC) Subject: [PATCH v3 14/40] cxl/core: Track port depth From: Dan Williams <dan.j.williams@intel.com> To: linux-cxl@vger.kernel.org Cc: Ben Widawsky <ben.widawsky@intel.com>, linux-pci@vger.kernel.org, nvdimm@lists.linux.dev Date: Sun, 23 Jan 2022 16:29:53 -0800 Message-ID: <164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <164298411792.3018233.7493009997525360044.stgit@dwillia2-desk3.amr.corp.intel.com> References: <164298411792.3018233.7493009997525360044.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit
Series	CXL.mem Topology Discovery and Hotplug Support \| expand [v3,00/40] CXL.mem Topology Discovery and Hotplug Support [v3,01/40] cxl: Rename CXL_MEM to CXL_PCI [v3,02/40] cxl/pci: Implement Interface Ready Timeout [v3,03/40] cxl/pci: Defer mailbox status checks to command timeouts [v3,04/40] cxl: Flesh out register names [v3,05/40] cxl/pci: Add new DVSEC definitions [v3,06/40] cxl/acpi: Map component registers for Root Ports [v3,07/40] cxl: Introduce module_cxl_driver [v3,08/40] cxl/core/port: Rename bus.c to port.c [v3,09/40] cxl/decoder: Hide physical address information from non-root [v3,10/40] cxl/core: Convert decoder range to resource [v3,11/40] cxl/core/port: Clarify decoder creation [v3,12/40] cxl/core: Fix cxl_probe_component_regs() error message [v3,13/40] cxl/core/port: Make passthrough decoder init implicit [v3,14/40] cxl/core: Track port depth [v3,15/40] cxl: Prove CXL locking [v3,16/40] cxl/core/port: Use dedicated lock for decoder target list [v3,17/40] cxl/port: Introduce cxl_port_to_pci_bus() [v3,18/40] cxl/pmem: Introduce a find_cxl_root() helper [v3,19/40] cxl/port: Up-level cxl_add_dport() locking requirements to the caller [v3,20/40] cxl/pci: Rename pci.h to cxlpci.h [v3,21/40] cxl/core: Generalize dport enumeration in the core [v3,22/40] cxl/core/hdm: Add CXL standard decoder enumeration to the core [v3,23/40] cxl/core: Emit modalias for CXL devices [v3,24/40] cxl/port: Add a driver for 'struct cxl_port' objects [v3,25/40] cxl/core/port: Remove @host argument for dport + decoder enumeration [v3,26/40] cxl/pci: Store component register base in cxlds [v3,27/40] cxl/pci: Cache device DVSEC offset [v3,28/40] cxl/pci: Retrieve CXL DVSEC memory info [v3,29/40] cxl/pci: Implement wait for media active [v3,30/40] cxl/pci: Emit device serial number [v3,31/40] cxl/memdev: Add numa_node attribute [v3,32/40] cxl/core/port: Add switch port enumeration [v3,33/40] cxl/mem: Add the cxl_mem driver [v3,34/40] cxl/core: Move target_list out of base decoder attributes [v3,35/40] cxl/core/port: Add endpoint decoders [v3,36/40] tools/testing/cxl: Mock dvsec_ranges() [v3,37/40] tools/testing/cxl: Fix root port to host bridge assignment [v3,38/40] tools/testing/cxl: Mock one level of switches [v3,39/40] tools/testing/cxl: Enumerate mock decoders [v3,40/40] tools/testing/cxl: Add a physical_node link

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164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com (mailing list archive)

State

Accepted

Commit

53fa1bff3426344d466d91e81f076eab677d0ece

Headers

Subject: [PATCH v3 14/40] cxl/core: Track port depth
From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>, linux-pci@vger.kernel.org,
 nvdimm@lists.linux.dev
Date: Sun, 23 Jan 2022 16:29:53 -0800
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 <164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com>
In-Reply-To: 
 <164298411792.3018233.7493009997525360044.stgit@dwillia2-desk3.amr.corp.intel.com>
References: 
 <164298411792.3018233.7493009997525360044.stgit@dwillia2-desk3.amr.corp.intel.com>
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Content-Type: text/plain; charset="utf-8"
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Series

CXL.mem Topology Discovery and Hotplug Support | expand

Commit Message

Dan Williams Jan. 24, 2022, 12:29 a.m. UTC

From: Ben Widawsky <ben.widawsky@intel.com>

In preparation for proving CXL subsystem usage of the device_lock()
order track the depth of ports with the expectation that  shallower port
locks can be held over deeper port locks.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/core/port.c |    2 ++
 drivers/cxl/cxl.h       |    2 ++
 2 files changed, 4 insertions(+)

Comments

Jonathan Cameron Jan. 31, 2022, 2:57 p.m. UTC | #1

On Sun, 23 Jan 2022 16:29:53 -0800
Dan Williams <dan.j.williams@intel.com> wrote:

> From: Ben Widawsky <ben.widawsky@intel.com>
> 
> In preparation for proving CXL subsystem usage of the device_lock()
> order track the depth of ports with the expectation that  shallower port

It's nitpick Monday: double space before shallower.

> locks can be held over deeper port locks.
> 
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/core/port.c |    2 ++
>  drivers/cxl/cxl.h       |    2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 826b300ba950..4ec5febf73fb 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -362,6 +362,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
>  	if (IS_ERR(port))
>  		return port;
>  
> +	if (parent_port)
> +		port->depth = parent_port->depth + 1;
>  	dev = &port->dev;
>  	if (parent_port)
>  		rc = dev_set_name(dev, "port%d", port->id);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index e60878ab4569..c1dc53492773 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -252,6 +252,7 @@ struct cxl_walk_context {
>   * @dports: cxl_dport instances referenced by decoders
>   * @decoder_ida: allocator for decoder ids
>   * @component_reg_phys: component register capability base address (optional)
> + * @depth: How deep this port is relative to the root. depth 0 is the root.
>   */
>  struct cxl_port {
>  	struct device dev;
> @@ -260,6 +261,7 @@ struct cxl_port {
>  	struct list_head dports;
>  	struct ida decoder_ida;
>  	resource_size_t component_reg_phys;
> +	unsigned int depth;
>  };
>  
>  /**
>

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 826b300ba950..4ec5febf73fb 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -362,6 +362,8 @@  struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
 	if (IS_ERR(port))
 		return port;
 
+	if (parent_port)
+		port->depth = parent_port->depth + 1;
 	dev = &port->dev;
 	if (parent_port)
 		rc = dev_set_name(dev, "port%d", port->id);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index e60878ab4569..c1dc53492773 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -252,6 +252,7 @@  struct cxl_walk_context {
  * @dports: cxl_dport instances referenced by decoders
  * @decoder_ida: allocator for decoder ids
  * @component_reg_phys: component register capability base address (optional)
+ * @depth: How deep this port is relative to the root. depth 0 is the root.
  */
 struct cxl_port {
 	struct device dev;
@@ -260,6 +261,7 @@  struct cxl_port {
 	struct list_head dports;
 	struct ida decoder_ida;
 	resource_size_t component_reg_phys;
+	unsigned int depth;
 };
 
 /**

[v3,14/40] cxl/core: Track port depth

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