@@ -2,6 +2,7 @@
/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/workqueue.h>
+#include <linux/genalloc.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/pci.h>
@@ -469,6 +470,24 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, CXL);
+struct cxl_port *devm_cxl_add_endpoint_port(struct device *host,
+ struct device *uport,
+ resource_size_t component_reg_phys,
+ u64 capacity, u64 pmem_offset,
+ struct cxl_port *parent_port)
+{
+ struct cxl_port *ep =
+ devm_cxl_add_port(host, uport, component_reg_phys, parent_port);
+ if (IS_ERR(ep) || !capacity)
+ return ep;
+
+ ep->capacity = capacity;
+ ep->pmem_offset = pmem_offset;
+
+ return ep;
+}
+EXPORT_SYMBOL_NS_GPL(devm_cxl_add_endpoint_port, CXL);
+
struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port)
{
/* There is no pci_bus associated with a CXL platform-root port */
@@ -309,6 +309,9 @@ struct cxl_nvdimm {
* @component_reg_phys: component register capability base address (optional)
* @dead: last ep has been removed, force port re-creation
* @depth: How deep this port is relative to the root. depth 0 is the root.
+ * @capacity: How much total storage the media can hold (endpoint only)
+ * @pmem_offset: Partition dividing volatile, [0, pmem_offset -1 ], and persistent
+ * [pmem_offset, capacity - 1] addresses.
*/
struct cxl_port {
struct device dev;
@@ -320,6 +323,9 @@ struct cxl_port {
resource_size_t component_reg_phys;
bool dead;
unsigned int depth;
+
+ u64 capacity;
+ u64 pmem_offset;
};
/**
@@ -368,6 +374,11 @@ struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
resource_size_t component_reg_phys,
struct cxl_port *parent_port);
+struct cxl_port *devm_cxl_add_endpoint_port(struct device *host,
+ struct device *uport,
+ resource_size_t component_reg_phys,
+ u64 capacity, u64 pmem_offset,
+ struct cxl_port *parent_port);
struct cxl_port *find_cxl_root(struct device *dev);
int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
int cxl_bus_rescan(void);
@@ -50,9 +50,12 @@ static int create_endpoint(struct cxl_memdev *cxlmd,
{
struct cxl_dev_state *cxlds = cxlmd->cxlds;
struct cxl_port *endpoint;
+ u64 partition = range_len(&cxlds->ram_range);
+ u64 size = range_len(&cxlds->ram_range) + range_len(&cxlds->pmem_range);
- endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
- cxlds->component_reg_phys, parent_port);
+ endpoint = devm_cxl_add_endpoint_port(&parent_port->dev, &cxlmd->dev,
+ cxlds->component_reg_phys, size,
+ partition, parent_port);
if (IS_ERR(endpoint))
return PTR_ERR(endpoint);
CXL Type 2 and 3 endpoints may contain Host-managed Device Memory (HDM). This memory can be either volatile, persistent, or some combination of both. Similar to the root decoder the port's resources can be considered the host memory of which decoders allocate out of. Unlike the root decoder resource, device resources are in the device physical address space domain. The CXL specification mandates a specific partitioning of volatile vs. persistent capacities. While an endpoint may contain one, or both capacities the volatile capacity while always be first. To accommodate this, two parameters are added to port creation, the offset of the split, and the total capacity. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- drivers/cxl/core/port.c | 19 +++++++++++++++++++ drivers/cxl/cxl.h | 11 +++++++++++ drivers/cxl/mem.c | 7 +++++-- 3 files changed, 35 insertions(+), 2 deletions(-)