From patchwork Thu Nov 7 20:58:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 13867113 X-Patchwork-Delegate: iweiny@gmail.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDF2C21B451 for ; Thu, 7 Nov 2024 20:58:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731013134; cv=none; b=HT6EWEPE7E+dB34HYW4F5qtUQYuXDHbmaJwiENAMN1SNbC6UTheG3IDgCIR2y8d8PkFphzqnO3eJEjqSh7viy1LnbFR7JhlYIfS3HkC3eVKVaxQ8bSjczXLM00FO6ix7EAYP8vi3Pbu0V3hD475rDxo2cpfdA+OQmvvRAbeNpmo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731013134; c=relaxed/simple; bh=iKXekMnJns1r1l4MIAOtOAM/J89hYV0EkfJDrmoDjyw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qLWak4YVUwWcKlENLNwxVnECjPfUANjQQedBhf9Txbeey/hioUHiW4N0zar3h+Xmc0ZY8NTayxblSJmzktVTNFyFQLwn/kwejbVZOmHuCuWcSqNdS9lqWhlS85s8DU3H513u7utwd1jFGWKHCa+opV8/gD6jjxOt+TKBeHVG8wI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lTTbzILL; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lTTbzILL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731013133; x=1762549133; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=iKXekMnJns1r1l4MIAOtOAM/J89hYV0EkfJDrmoDjyw=; b=lTTbzILLZCOYHjf3DIvJ0vcTUZN0DXU8WNgp9GIR64IM3Cjmey0Gc0G+ 4oL2khJwaf2jlqgECQThUezKS2xq9KGkq6ED5d/E6IZKXjGTvQl0pY2Re 65YFC+m34MgrXgl18mTqn3p1jeTLUdLBT3AtaApobwnlFrQpN7Sor2QfK af0k4r6S41kbpV+4GAtAXCY0oBC9AuWKwvB1upbySbUP79ILLrElYB8AP 12K/CV2JW+mEOGz6Fr4GWrqhQny/aNjGMIKwwEviakcwuPHwqnqSK031y iLdAvCcrBLawEgFoao6AhFZwrmdaayZX6r3iXPpAaXkOsih8+hRr3t+3H w==; X-CSE-ConnectionGUID: 90yHEjqJRGiD3PgkEMwLFg== X-CSE-MsgGUID: EYDLYxrARi2c2ebu7HpHYQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41440999" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41440999" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 12:58:52 -0800 X-CSE-ConnectionGUID: phfWLpxQTU+VtcHdcqb3zw== X-CSE-MsgGUID: mZMEyibeREKILnYQTEbAlA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,136,1728975600"; d="scan'208";a="122745997" Received: from aschofie-mobl2.amr.corp.intel.com (HELO localhost) ([10.125.110.195]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 12:58:51 -0800 From: ira.weiny@intel.com Date: Thu, 07 Nov 2024 14:58:28 -0600 Subject: [PATCH v7 10/27] cxl/region: Add dynamic capacity decoder and region modes Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241107-dcd-type2-upstream-v7-10-56a84e66bc36@intel.com> References: <20241107-dcd-type2-upstream-v7-0-56a84e66bc36@intel.com> In-Reply-To: <20241107-dcd-type2-upstream-v7-0-56a84e66bc36@intel.com> To: Dave Jiang , Fan Ni , Jonathan Cameron , Navneet Singh , Jonathan Corbet , Andrew Morton Cc: Dan Williams , Davidlohr Bueso , Alison Schofield , Vishal Verma , Ira Weiny , linux-cxl@vger.kernel.org, linux-doc@vger.kernel.org, nvdimm@lists.linux.dev, linux-kernel@vger.kernel.org, Li Ming X-Mailer: b4 0.15-dev-2a633 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731013104; l=3535; i=ira.weiny@intel.com; s=20221211; h=from:subject:message-id; bh=92oV6LOz1B7q9oFrHHDLBvhNO1dz+h3J4p0UZ4tMspw=; b=bm69Txz7OvoU0AeJo1Seg7enjh3GGYcq8gGWWkdVObqNsO9ShDqJAdltazxinDU31E2pGO4G3 xkjzVvXRcZwCc2i7CRWJpLe2vTBWDDDuUuzs76dknwQeZqCVc4Vzf2+ X-Developer-Key: i=ira.weiny@intel.com; a=ed25519; pk=noldbkG+Wp1qXRrrkfY1QJpDf7QsOEthbOT7vm0PqsE= From: Navneet Singh One or more decoders each pointing to a Dynamic Capacity (DC) partition form a CXL software region. The region mode reflects composition of that entire software region. Decoder mode reflects a specific DC partition. DC partitions are also known as DC regions per CXL specification v3.1. Define the new modes and helper functions required to make the association between these new modes. Reviewed-by: Jonathan Cameron Reviewed-by: Fan Ni Reviewed-by: Dave Jiang Reviewed-by: Li Ming Signed-off-by: Navneet Singh Link: https://lore.kernel.org/all/663922b475e50_d54d72945b@dwillia2-xfh.jf.intel.com.notmuch/ [1] Suggested-by: Dan Williams Co-developed-by: Ira Weiny Signed-off-by: Ira Weiny --- drivers/cxl/core/region.c | 4 ++++ drivers/cxl/cxl.h | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index b3beab787faeb552850ac3839472319fcf8f2835..2ca6148d108cc020bebcb34b09028fa59bb62f02 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1870,6 +1870,8 @@ static bool cxl_modes_compatible(enum cxl_region_mode rmode, return true; if (rmode == CXL_REGION_PMEM && dmode == CXL_DECODER_PMEM) return true; + if (rmode == CXL_REGION_DC && cxl_decoder_mode_is_dc(dmode)) + return true; return false; } @@ -3233,6 +3235,8 @@ cxl_decoder_to_region_mode(enum cxl_decoder_mode mode) return CXL_REGION_RAM; case CXL_DECODER_PMEM: return CXL_REGION_PMEM; + case CXL_DECODER_DC0 ... CXL_DECODER_DC7: + return CXL_REGION_DC; case CXL_DECODER_MIXED: default: return CXL_REGION_MIXED; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 5d74eb4ffab3ea2656c8e3c0563b8d7b69d76232..f931ebdd36d05a8aa758627746f0fa425a5f14fd 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -370,6 +370,14 @@ enum cxl_decoder_mode { CXL_DECODER_NONE, CXL_DECODER_RAM, CXL_DECODER_PMEM, + CXL_DECODER_DC0, + CXL_DECODER_DC1, + CXL_DECODER_DC2, + CXL_DECODER_DC3, + CXL_DECODER_DC4, + CXL_DECODER_DC5, + CXL_DECODER_DC6, + CXL_DECODER_DC7, CXL_DECODER_MIXED, CXL_DECODER_DEAD, }; @@ -380,6 +388,14 @@ static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) [CXL_DECODER_NONE] = "none", [CXL_DECODER_RAM] = "ram", [CXL_DECODER_PMEM] = "pmem", + [CXL_DECODER_DC0] = "dc0", + [CXL_DECODER_DC1] = "dc1", + [CXL_DECODER_DC2] = "dc2", + [CXL_DECODER_DC3] = "dc3", + [CXL_DECODER_DC4] = "dc4", + [CXL_DECODER_DC5] = "dc5", + [CXL_DECODER_DC6] = "dc6", + [CXL_DECODER_DC7] = "dc7", [CXL_DECODER_MIXED] = "mixed", }; @@ -388,10 +404,16 @@ static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) return "mixed"; } +static inline bool cxl_decoder_mode_is_dc(enum cxl_decoder_mode mode) +{ + return (mode >= CXL_DECODER_DC0 && mode <= CXL_DECODER_DC7); +} + enum cxl_region_mode { CXL_REGION_NONE, CXL_REGION_RAM, CXL_REGION_PMEM, + CXL_REGION_DC, CXL_REGION_MIXED, }; @@ -401,6 +423,7 @@ static inline const char *cxl_region_mode_name(enum cxl_region_mode mode) [CXL_REGION_NONE] = "none", [CXL_REGION_RAM] = "ram", [CXL_REGION_PMEM] = "pmem", + [CXL_REGION_DC] = "dc", [CXL_REGION_MIXED] = "mixed", };