From patchwork Fri Sep 18 23:42:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tyler Baker X-Patchwork-Id: 7221231 Return-Path: X-Original-To: patchwork-linux-nvdimm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 28728BEEC1 for ; Fri, 18 Sep 2015 23:42:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EABDE20983 for ; Fri, 18 Sep 2015 23:42:20 +0000 (UTC) Received: from ml01.01.org (ml01.01.org [198.145.21.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9704C20999 for ; Fri, 18 Sep 2015 23:42:19 +0000 (UTC) Received: from ml01.vlan14.01.org (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 78F9661819; Fri, 18 Sep 2015 16:42:19 -0700 (PDT) X-Original-To: linux-nvdimm@lists.01.org Delivered-To: linux-nvdimm@lists.01.org Received: from mail-qg0-f41.google.com (mail-qg0-f41.google.com [209.85.192.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EF30B61813 for ; Fri, 18 Sep 2015 16:42:17 -0700 (PDT) Received: by qgez77 with SMTP id z77so51671605qge.1 for ; Fri, 18 Sep 2015 16:42:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=029OTH4RQmiaWWvGSrvE5i4Dn491YWaw562HyNZVQps=; b=IfX9jvD3yDrbr3tGShU+6SU45OmFsBt4F+Lq+dmM6yvsTCWhZjFaMdBYAiR9DDN0g0 fLvF2Ai5ws8SkTNiqzhOjUFhljh/mlzt8n7xqaZEQDCp9Lnl3G4nHohrHVn01eK/mlq5 WHDkD9EvYN6zrskKyP2rFYrRgTo+huCaAcrqwAGDa/oRiZnOx+P6GNFcltG3FvNN/Bpb b+FqKZvGgFFcG37D0LzXy1FmDUwwrf0T0na0+gBFBRFwUnapEXo2nDxbygOKsowq5yMG AfZ8yxGw2Asmr7tTMjjvbq4yBoqm83juenu5UqjE+y1u9CoBh3MYEXLKSTvBPwbr+gPi Aa3Q== X-Gm-Message-State: ALoCoQnwhVTaJbdJUI7NzQiTPj03Ko/ztctFcyvmywaSa40kaemrg15pd6SDO2nMv1Gedm1w1NpJ MIME-Version: 1.0 X-Received: by 10.140.93.53 with SMTP id c50mr9477329qge.59.1442619736868; Fri, 18 Sep 2015 16:42:16 -0700 (PDT) Received: by 10.55.3.21 with HTTP; Fri, 18 Sep 2015 16:42:16 -0700 (PDT) In-Reply-To: <20150826012735.8851.49787.stgit@dwillia2-desk3.amr.corp.intel.com> References: <20150826010220.8851.18077.stgit@dwillia2-desk3.amr.corp.intel.com> <20150826012735.8851.49787.stgit@dwillia2-desk3.amr.corp.intel.com> Date: Fri, 18 Sep 2015 16:42:16 -0700 Message-ID: Subject: Re: [PATCH v2 2/9] mm: move __phys_to_pfn and __pfn_to_phys to asm/generic/memory_model.h From: Tyler Baker To: Dan Williams Cc: linux-nvdimm@lists.01.org, Kevin's boot bot , david@fromorbit.com, "linux-kernel@vger.kernel.org" , Ingo Molnar , linux-mm@kvack.org, hpa@zytor.com, hch@lst.de X-BeenThere: linux-nvdimm@lists.01.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "Linux-nvdimm developer list." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linux-nvdimm-bounces@lists.01.org Sender: "Linux-nvdimm" X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, On 25 August 2015 at 18:27, Dan Williams wrote: > From: Christoph Hellwig > > Three architectures already define these, and we'll need them genericly > soon. > > Signed-off-by: Christoph Hellwig > Signed-off-by: Dan Williams > --- > arch/arm/include/asm/memory.h | 6 ------ > arch/arm64/include/asm/memory.h | 6 ------ > arch/unicore32/include/asm/memory.h | 6 ------ > include/asm-generic/memory_model.h | 6 ++++++ > 4 files changed, 6 insertions(+), 18 deletions(-) > > diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h > index b7f6fb462ea0..98d58bb04ac5 100644 > --- a/arch/arm/include/asm/memory.h > +++ b/arch/arm/include/asm/memory.h > @@ -119,12 +119,6 @@ > #endif > > /* > - * Convert a physical address to a Page Frame Number and back > - */ > -#define __phys_to_pfn(paddr) ((unsigned long)((paddr) >> PAGE_SHIFT)) > -#define __pfn_to_phys(pfn) ((phys_addr_t)(pfn) << PAGE_SHIFT) > - > -/* > * Convert a page to/from a physical address > */ > #define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page))) > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h > index f800d45ea226..d808bb688751 100644 > --- a/arch/arm64/include/asm/memory.h > +++ b/arch/arm64/include/asm/memory.h > @@ -81,12 +81,6 @@ > #define __phys_to_virt(x) ((unsigned long)((x) - PHYS_OFFSET + PAGE_OFFSET)) > > /* > - * Convert a physical address to a Page Frame Number and back > - */ > -#define __phys_to_pfn(paddr) ((unsigned long)((paddr) >> PAGE_SHIFT)) > -#define __pfn_to_phys(pfn) ((phys_addr_t)(pfn) << PAGE_SHIFT) > - > -/* > * Convert a page to/from a physical address > */ > #define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page))) > diff --git a/arch/unicore32/include/asm/memory.h b/arch/unicore32/include/asm/memory.h > index debafc40200a..3bb0a29fd2d7 100644 > --- a/arch/unicore32/include/asm/memory.h > +++ b/arch/unicore32/include/asm/memory.h > @@ -61,12 +61,6 @@ > #endif > > /* > - * Convert a physical address to a Page Frame Number and back > - */ > -#define __phys_to_pfn(paddr) ((paddr) >> PAGE_SHIFT) > -#define __pfn_to_phys(pfn) ((pfn) << PAGE_SHIFT) > - > -/* > * Convert a page to/from a physical address > */ > #define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page))) > diff --git a/include/asm-generic/memory_model.h b/include/asm-generic/memory_model.h > index 14909b0b9cae..f20f407ce45d 100644 > --- a/include/asm-generic/memory_model.h > +++ b/include/asm-generic/memory_model.h > @@ -69,6 +69,12 @@ > }) > #endif /* CONFIG_FLATMEM/DISCONTIGMEM/SPARSEMEM */ > > +/* > + * Convert a physical address to a Page Frame Number and back > + */ > +#define __phys_to_pfn(paddr) ((unsigned long)((paddr) >> PAGE_SHIFT)) > +#define __pfn_to_phys(pfn) ((pfn) << PAGE_SHIFT) The kernelci.org bot has been reporting complete boot failures[1] on ARM platforms with more than 4GB of memory and LPAE enabled. I've bisected[2] the failures down to this commit, and reverting it on top of the latest mainline resolves the boot issue. I took a closer look at this patch and noticed the cast to phys_addr_t was dropped in the generic function. Adding this to the new generic function solves the boot issue I'm reporting. If this fix is valid, I can send a formal patch or it can be squashed into the original commit. Cheers, Tyler [1] http://kernelci.org/boot/?d01&LPAE [2] http://hastebin.com/tuhefudage.vhdl diff --git a/include/asm-generic/memory_model.h b/include/asm-generic/memory_model.h index f20f407..db9f5c7 100644 --- a/include/asm-generic/memory_model.h +++ b/include/asm-generic/memory_model.h @@ -73,7 +73,7 @@ * Convert a physical address to a Page Frame Number and back */ #define __phys_to_pfn(paddr) ((unsigned long)((paddr) >> PAGE_SHIFT)) -#define __pfn_to_phys(pfn) ((pfn) << PAGE_SHIFT) +#define __pfn_to_phys(pfn) ((phys_addr_t)(pfn) << PAGE_SHIFT) #define page_to_pfn __page_to_pfn #define pfn_to_page __pfn_to_page