From patchwork Mon Dec 9 09:21:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 11278669 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B0BC2139A for ; Mon, 9 Dec 2019 09:20:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8F8072075B for ; Mon, 9 Dec 2019 09:20:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="LDRSB5vT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727501AbfLIJUv (ORCPT ); Mon, 9 Dec 2019 04:20:51 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:49442 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726377AbfLIJUu (ORCPT ); Mon, 9 Dec 2019 04:20:50 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kgt1025891; Mon, 9 Dec 2019 03:20:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575883242; bh=dmmRTLHcKKOhWpZ8gdUFaYUVoMPoJ3qut66Ws5fy6ZI=; h=From:To:CC:Subject:Date; b=LDRSB5vTC1A1kbf1luw+acC1iBRooExqA3ZIBN7nt/QZ7oK41NNG5FnCcGiareWWL 3ii3rtK1ZWbGFX/l23Jm9pTQu/RKEmeCLc8zd7frGE9fzoc74IAObIdTfRegAoc9MV uR8BlKAVNvp385qooITx39/4dtOSAwhIeNiQjZfY= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB99Kgkc004900 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Dec 2019 03:20:42 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 9 Dec 2019 03:20:42 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 9 Dec 2019 03:20:42 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB99Kccw087697; Mon, 9 Dec 2019 03:20:39 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , , Kishon Vijay Abraham I Subject: [PATCH 00/13] Add PCIe support to TI's J721E SoC Date: Mon, 9 Dec 2019 14:51:34 +0530 Message-ID: <20191209092147.22901-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org TI's J721E SoC uses Cadence PCIe core to implement both RC mode and EP mode. The high level features are: *) Supports Legacy, MSI and MSI-X interrupt *) Supports upto GEN4 speed mode *) Supports SR-IOV *) Supports multiple physical function *) Ability to route all transactions via SMMU This patch series *) Add support in Cadence PCIe core to be used for TI's J721E SoC *) Add a driver for J721E PCIe wrapper This is a trimmed down series of the initial RFC series [1]. Changes from RFC [1]: *) Ability to route all transactions via SMMU is removed *) SR-IOV support is removed *) Miscellaneous improvement to endpoint core is removed All these will be sent as smaller series. I've also pushed the series along with device tree changes [2]. [1] -> https://lkml.org/lkml/2019/6/4/619 [2] -> https://github.com/kishon/linux-wip.git j7_pci_v1 Kishon Vijay Abraham I (13): PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path linux/kernel.h: Add PTR_ALIGN_DOWN macro PCI: cadence: Add support to use custom read and write accessors PCI: cadence: Add support to start link and verify link status PCI: cadence: Add read and write accessors to perform only 32-bit accesses PCI: cadence: Allow pci_host_bridge to have custom pci_ops PCI: cadence: Add new *ops* for CPU addr fixup PCI: cadence: Use local management register to configure Vendor ID dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC PCI: j721e: Add TI J721E PCIe driver misc: pci_endpoint_test: Add J721E in pci_device_id table MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe .../bindings/pci/ti,j721e-pci-ep.yaml | 113 +++++ .../bindings/pci/ti,j721e-pci-host.yaml | 161 +++++++ MAINTAINERS | 3 +- drivers/misc/pci_endpoint_test.c | 9 + drivers/pci/controller/cadence/Kconfig | 23 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-j721e.c | 430 ++++++++++++++++++ .../pci/controller/cadence/pcie-cadence-ep.c | 10 +- .../controller/cadence/pcie-cadence-host.c | 55 ++- drivers/pci/controller/cadence/pcie-cadence.c | 48 +- drivers/pci/controller/cadence/pcie-cadence.h | 133 +++++- include/linux/kernel.h | 1 + 12 files changed, 958 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml create mode 100644 drivers/pci/controller/cadence/pci-j721e.c