From patchwork Wed May 14 11:36:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 4174251 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1F7E1BFF02 for ; Wed, 14 May 2014 11:37:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 538882037B for ; Wed, 14 May 2014 11:37:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 647F32035D for ; Wed, 14 May 2014 11:37:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754939AbaENLhI (ORCPT ); Wed, 14 May 2014 07:37:08 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:44683 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751442AbaENLhH (ORCPT ); Wed, 14 May 2014 07:37:07 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s4EBafZv009471; Wed, 14 May 2014 06:36:41 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4EBaeWM016368; Wed, 14 May 2014 06:36:40 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 14 May 2014 06:36:40 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4EBacWi008284; Wed, 14 May 2014 06:36:38 -0500 From: Sekhar Nori To: Tony Lindgren , Benoit Cousson CC: Linux OMAP Mailing List , Linux ARM Mailing List , Device Tree Mailing List , Tero Kristo Subject: [PATCH] ARM: dts: AM4372: clk: efuse based crystal frequency detect Date: Wed, 14 May 2014 17:06:37 +0530 Message-ID: <062e8a534b1e372db7ed3daa3df7e3c5b885ffab.1400062517.git.nsekhar@ti.com> X-Mailer: git-send-email 1.7.10.1 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Afzal Mohammed Currently oscillator frequency is determined based on sysboot settings, it may not be the case always. To determine it properly, efuse settings also has to be read. CONTROL_STATUS register holds this information. Bit 31: if 0, frequency to be determined based on sysboot if 1, frequency to be determined based on efuse Bit 29,30 - for efuse detection of frequency Bit 22,23 - for sysboot detection of frequency Add clock nodes (mux) to determine oscillator frequency as above. Signed-off-by: Afzal Mohammed Acked-by: Tero Kristo Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/am43xx-clocks.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 142009c..71b029c 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -11,6 +11,22 @@ sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; + clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; + ti,bit-shift = <31>; + reg = <0x0040>; + }; + + crystal_freq_sel_ck: crystal_freq_sel_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <29>; + reg = <0x0040>; + }; + + sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>;