From patchwork Wed Apr 1 06:42:54 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalle Jokiniemi X-Patchwork-Id: 15586 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n316hWxI003337 for ; Wed, 1 Apr 2009 06:43:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757828AbZDAGm6 (ORCPT ); Wed, 1 Apr 2009 02:42:58 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1758386AbZDAGm6 (ORCPT ); Wed, 1 Apr 2009 02:42:58 -0400 Received: from smtp1.digia.com ([82.118.214.156]:31727 "EHLO smtp1.digia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751009AbZDAGm5 (ORCPT ); Wed, 1 Apr 2009 02:42:57 -0400 Received: from smtp1.digia.com (unknown [127.0.0.1]) by IMSA (Postfix) with ESMTP id C8DF947804B; Wed, 1 Apr 2009 09:42:53 +0300 (EEST) Received: from IT-EXCH02-HKI.it.local (unknown [10.9.52.55]) by smtp1.digia.com (Postfix) with ESMTP id BCB6F478049; Wed, 1 Apr 2009 09:42:53 +0300 (EEST) Received: from localhost.localdomain (10.120.146.225) by IT-EXCH02-HKI.it.local (10.9.52.56) with Microsoft SMTP Server id 8.1.340.0; Wed, 1 Apr 2009 09:42:53 +0300 From: Kalle Jokiniemi To: , CC: , Kalle Jokiniemi Subject: [PATCH] ARM: OMAP3: Fix HW SAVEANDRESTORE shift define Date: Wed, 1 Apr 2009 09:42:54 +0300 Message-ID: <1238568174-28291-2-git-send-email-kalle.jokiniemi@digia.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1238568174-28291-1-git-send-email-kalle.jokiniemi@digia.com> References: <> <1238568174-28291-1-git-send-email-kalle.jokiniemi@digia.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: IMSS-7.0.0.1085-5.6.0.1016-16554.004 X-TM-AS-Result: No--6.821-8.0-31-1 X-imss-scan-details: No--6.821-8.0-31-1 X-TM-AS-User-Approved-Sender: No Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The OMAP3430ES2_SAVEANDRESTORE_SHIFT macro is used by powerdomain code in "1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT" manner, but the definition was also (1 << 4), meaning we actually modified bit 16. So the definition needs to be 4. This fixes also a cold reset HW bug in OMAP3430 ES3.x where some of the efuse bits are not isolated during wake-up from off mode. This can cause randomish cold resets with off mode. Enabling the USBTLL hardware SAVEANDRESTORE causes the core power up assert to be delayed in a way that we will not get faulty values when boot ROM is reading the unisolated registers. Signed-off-by: Kalle Jokiniemi Acked-by: Kevin Hilman Acked-by: Paul Walmsley --- arch/arm/mach-omap2/prm-regbits-34xx.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index d73eee8..d792c29 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -409,7 +409,7 @@ /* PM_PREPWSTST_CAM specific bits */ /* PM_PWSTCTRL_USBHOST specific bits */ -#define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4) +#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 /* RM_RSTST_PER specific bits */