From patchwork Thu Oct 15 14:48:50 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 54039 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n9FEnoEe002568 for ; Thu, 15 Oct 2009 14:49:53 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762210AbZJOOtf (ORCPT ); Thu, 15 Oct 2009 10:49:35 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1762198AbZJOOte (ORCPT ); Thu, 15 Oct 2009 10:49:34 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:56023 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762196AbZJOOte (ORCPT ); Thu, 15 Oct 2009 10:49:34 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id n9FEmsvN022939 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 15 Oct 2009 09:48:56 -0500 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id n9FEmpA9010219; Thu, 15 Oct 2009 20:18:52 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id n9FEmpW3014353; Thu, 15 Oct 2009 20:18:51 +0530 Received: (from x0016154@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id n9FEmpBu014351; Thu, 15 Oct 2009 20:18:51 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, Rajendra Nayak Subject: [PATCH v2 2/2] OMAP3: PM: Configure CPUidle latencies/thresholds from board file Date: Thu, 15 Oct 2009 20:18:50 +0530 Message-Id: <1255618130-14005-2-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1255618130-14005-1-git-send-email-rnayak@ti.com> References: <1255618130-14005-1-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 0f1975c..d2b2f8f 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -73,6 +73,24 @@ static struct prm_setup_vc omap3_setuptime_table = { .vdd1_off = 0x00, }; +/* FIXME: These values need to be updated based on more profiling on 3430sdp*/ +static struct cpuidle_params omap3_cpuidle_params_table[] = { + /* C1 */ + {2, 2, 5}, + /* C2 */ + {10, 10, 30}, + /* C3 */ + {50, 50, 300}, + /* C4 */ + {1500, 1800, 4000}, + /* C5 */ + {2500, 7500, 12000}, + /* C6 */ + {3000, 8500, 15000}, + /* C7 */ + {10000, 30000, 300000}, +}; + static int board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_RIGHT), @@ -203,6 +221,7 @@ static void __init omap_3430sdp_init_irq(void) omap_board_config = sdp3430_config; omap_board_config_size = ARRAY_SIZE(sdp3430_config); omap3_pm_init_vc(&omap3_setuptime_table); + omap3_pm_init_cpuidle(omap3_cpuidle_params_table); omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL, omap3_mpu_rate_table, omap3_dsp_rate_table, omap3_l3_rate_table); omap_init_irq(); diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index c44a942..f5d8f55 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -60,6 +60,30 @@ struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; struct omap3_processor_cx current_cx_state; struct powerdomain *mpu_pd, *core_pd, *per_pd; +/* + * The latencies/thresholds for various C states have + * to be configured from the respective board files. + * These are some default values (which might not provide + * the best power savings) used on boards which do not + * pass these details from the board file. + */ +static struct cpuidle_params cpuidle_params_table[] = { + /* C1 */ + {2, 2, 5}, + /* C2 */ + {10, 10, 30}, + /* C3 */ + {50, 50, 300}, + /* C4 */ + {1500, 1800, 4000}, + /* C5 */ + {2500, 7500, 12000}, + /* C6 */ + {3000, 8500, 15000}, + /* C7 */ + {10000, 30000, 300000}, +}; + static int omap3_idle_bm_check(void) { if (!omap3_can_sleep()) @@ -165,6 +189,24 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); +void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) +{ + int i; + + if (!cpuidle_board_params) + return; + + for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { + cpuidle_params_table[i].sleep_latency = + cpuidle_board_params[i].sleep_latency; + cpuidle_params_table[i].wake_latency = + cpuidle_board_params[i].wake_latency; + cpuidle_params_table[i].threshold = + cpuidle_board_params[i].threshold; + } + return; +} + /* omap3_init_power_states - Initialises the OMAP3 specific C states. * * Below is the desciption of each C state. diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index ca673c5..0b814ab 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -41,7 +41,15 @@ struct prm_setup_vc { u16 vdd1_ret; u16 vdd1_off; }; + +struct cpuidle_params { + u32 sleep_latency; + u32 wake_latency; + u32 threshold; +}; + extern void omap3_pm_init_vc(struct prm_setup_vc *setup_vc); +extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params); extern int resource_set_opp_level(int res, u32 target_level, int flags); extern int resource_access_opp_lock(int res, int delta);