@@ -94,6 +94,8 @@ u32 voltage_off_while_idle;
OMAP3430_ST_GPT5_MASK|OMAP3430_ST_GPT4_MASK|\
OMAP3430_ST_GPT3_MASK|OMAP3430_ST_GPT2_MASK)
+#define OTG_SYSCONFIG (OMAP34XX_HSUSB_OTG_BASE + 0x404)
+
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
@@ -423,6 +425,16 @@ static void restore_table_entry(void)
restore_control_register(control_reg_value);
}
+static inline void disable_otg_autoidle(void)
+{
+ /*
+ * OTG autoidle can prevent core domain sleep in some cases, thus
+ * disable it. See omap erratas 1.164 and 1.165.
+ */
+ cm_set_mod_reg_bits(OMAP3430_EN_HSOTGUSB, CORE_MOD, CM_ICLKEN1);
+ omap_writel(0x0, OTG_SYSCONFIG);
+}
+
void omap_sram_idle(void)
{
/* Variable to tell what needs to be saved and restored
@@ -628,6 +640,7 @@ void omap_sram_idle(void)
omap3_prcm_restore_context();
omap3_sram_restore_context();
omap2_sms_restore_context();
+ disable_otg_autoidle();
}
omap_uart_resume_idle(0);
omap_uart_resume_idle(1);
@@ -1417,6 +1430,7 @@ static int __init omap3_pm_early_init(void)
OMAP3_PRM_POLCTRL_OFFSET);
configure_vc();
+ disable_otg_autoidle();
return 0;
}