@@ -67,57 +67,6 @@ static const struct sdram_info rx51_info = {
.row_lines = 13,
};
-#define CM_BASE 0x48004000
-
-#define CM_CLKSEL_CORE 0x0a40
-#define CM_CLKSEL1_PLL 0x0d40
-
-#define PRM_CLKSEL 0x48306d40
-#define PRM_CLKSRC_CTRL 0x48307270
-
-static u32 cm_base = CM_BASE;
-
-static inline u32 cm_read_reg(int idx)
-{
- return *(u32 *)OMAP2_L4_IO_ADDRESS(cm_base + idx);
-}
-
-static const unsigned long sys_clk_rate_table[] = {
- 12000, 13000, 19200, 26000, 38400, 16800
-};
-
-static unsigned long get_sys_clk_rate(void)
-{
- unsigned long rate;
-
- rate = sys_clk_rate_table[*(u32 *)OMAP2_L4_IO_ADDRESS(PRM_CLKSEL) & 0x07];
- if (((*(u32 *)OMAP2_L4_IO_ADDRESS(PRM_CLKSRC_CTRL) >> 6) & 0x03) == 0x02)
- rate /= 2;
- return rate;
-}
-
-static unsigned long get_core_rate(void)
-{
- unsigned long rate;
- u32 l;
-
- l = cm_read_reg(CM_CLKSEL1_PLL);
- rate = get_sys_clk_rate();
- rate *= ((l >> 16) & 0x7ff);
- rate /= ((l >> 8) & 0x7f) + 1;
- rate /= (l >> 27) & 0x1f;
-
- return rate;
-}
-
-static unsigned long get_l3_rate(void)
-{
- u32 l;
-
- l = cm_read_reg(CM_CLKSEL_CORE);
- return get_core_rate() / (l & 0x03);
-}
-
static unsigned long sdrc_get_fclk_period(long rate)
{
/* In picoseconds */